
Rev. 5.0, 09/04, page xv of xviii
16.1.3 Input/Output Pins.................................................................................................564
16.1.4 Register Configuration.........................................................................................564
Register Descriptions........................................................................................................565
16.2.1 D/A Data Registers 0 and 1 (DADR0/1)..............................................................565
16.2.2 D/A Control Register (DACR).............................................................................565
16.2.3 D/A Standby Control Register (DASTCR)..........................................................567
Operation ..........................................................................................................................568
D/A Output Control ..........................................................................................................569
16.2
16.3
16.4
Section 17 RAM ................................................................................................571
17.1
Overview...........................................................................................................................571
17.1.1 Block Diagram.....................................................................................................571
17.1.2 Register Configuration.........................................................................................572
17.2
System Control Register (SYSCR)...................................................................................572
17.3
Operation ..........................................................................................................................573
Section 18 ROM ................................................................................................575
18.1
Features.............................................................................................................................575
18.2
Overview...........................................................................................................................577
18.2.1 Block Diagram.....................................................................................................577
18.2.2 Operating Mode...................................................................................................578
18.2.3 Mode Comparison................................................................................................579
18.2.4 Flash MAT Configuration....................................................................................581
18.2.5 Block Division.....................................................................................................581
18.2.6 Programming/Erasing Interface...........................................................................582
18.3
Pin Configuration..............................................................................................................585
18.4
Register Configuration......................................................................................................586
18.4.1 Registers...............................................................................................................586
18.4.2 Programming/Erasing Interface Register.............................................................589
18.4.3 Programming/Erasing Interface Parameter..........................................................595
18.4.4 RAM Control Register (RAMCR).......................................................................606
18.4.5 Flash Vector Address Control Register (FVACR)...............................................607
18.4.6 Flash Vector Address Data Register (FVADR)...................................................609
18.5
On-Board Programming Mode.........................................................................................610
18.5.1 Boot Mode...........................................................................................................610
18.5.2 User Program Mode.............................................................................................613
18.5.3 User Boot Mode...................................................................................................624
18.6
Protection..........................................................................................................................628
18.6.1 Hardware Protection............................................................................................628
18.6.2 Software Protection..............................................................................................629
18.6.3 Error Protection....................................................................................................630
18.7
Flash Memory Emulation in RAM ...................................................................................632
18.8
Switching between User MAT and User Boot MAT........................................................635