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參數(shù)資料
| 型號： | H8250 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Universal Asynchronous Receiver/Transmitter |
| 中文描述： | 通用異步接收器/發(fā)送器 |
| 文件頁數(shù)： | 6/7頁 |
| 文件大?。?/td> | 49K |
| 代理商： | H8250 |
CAST H8250 Megafunction Datasheet
CAST, Inc.
Page 6
RX Block
This is the receiver block. It handles the receiving of the incoming serial word. It is programmable to recognize
data widths such as 5, 6, 7 or 8 bits, various parity settings such as even, odd or no parity and different stop
bits of 1, 1 and 2 bits. It checks for errors in the input data stream such as overrun errors, frame errors,
parity errors and break errors. If the incoming word has no problems it is placed in the Receiver Holding
register.
I nterrupt Control
The Interrupt Control block sends an interrupt signal back to the processor depending on the state of the
received and transmitted data. There are various levels of interrupt which can be read from the Interrupt
Identification register, which gives the level of interrupt. Interrupts are sent in the condition of empty
transmission or receiving buffers, an error in the receiving of a character, or other conditions requiring the
attention of the processor.
Baud Rate Generator
This block takes the input clock, CLK, and divides it by a programmed value (from 1 to 2
16
– 1). This divided
clock is then divided by 16 to create the transmission clock called the Baudout clock. This clock can be
connected to the input clock (RCLK) to provide it with a proper clock.
TX Block
The Transmit block handles the transmission of data written to the Transmission Holding register. It adds
required start, parity and stop bits to the data being transmitted so that the receiving device can do the proper
error handling and receiving.
Component Substitution
The H8250 megafunction is modeled after the Intel 8250. The following points differentiate the H8250 from the
Intel device. In order to create a megafunction with the same functions a wrapper is required. A sample
wrapper is included.
No provision is made for a crystal. The CLK input is designed to accept a standard digital input.
The bi-directional Data Bus has been split into an input and an output component. In order to use the
megafunction with a bi-directional Data Bus, the DDIS signal can be used as the controlling signal for the
tri-state drivers.
RD2, WR2, CS1 and CS2 have been eliminated. A single signal takes their place. These are RD, WR and CS.
The ADSN signal has been removed. The H8250 functions as if the ADSN signal is held low. The included
wrapper can be used to add the ADSN functionality latching the address and data buses.
The main clock input CLK must be active from power-up.
The Baudrate Generator is reset to the 0001h value upon activation of the MR signal. Programming the BRG
to 0000h is an illegal value. The minimum value for the BRG is 0001h. The Output Data Bus always shows
the value of the last register read.
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