CL
參數(shù)資料
型號: GTLP16612MTDX
廠商: Fairchild Semiconductor
文件頁數(shù): 7/9頁
文件大?。?/td> 0K
描述: IC UNIV BUS TXRX 18BIT 56TSSOP
標(biāo)準(zhǔn)包裝: 1,000
系列: 74GTLP
邏輯類型: 通用總線收發(fā)器
電路數(shù): 18 位
輸出電流高,低: 32mA,32mA
電源電壓: 3.15 V ~ 3.45 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 56-TSSOP
包裝: 帶卷 (TR)
7
www.fairchildsemi.com
GTLP166
12
Test Circuits and Timing Waveforms
Test Circuit for A Outputs
CL includes probes and jig capacitance.
Test Circuit for B Outputs
CL includes probes and jig capacitance.
For B Port outputs, CL = 30 pF is used for
worst case edge rate.
Voltage Waveforms Pulse Duration
(Vm
= 1.5V for A Port and 1.0V for B Port)
Voltage Waveforms Setup and Hold Times
(Vm
= 1.5V for A Port and 1.0V for B Port)
Voltage Waveforms Propagation Delay Times
(A Port to B Port)
Voltage Waveforms Propagation Delay Times
(B Port to A Port)
All input pulses have the following characteristics: frequency
= 10 MHz, t
r = tf = 2 ns, ZO = 50. The outputs are measured
one at a time with one transition per measurement.
Voltage Waveforms Enable and Disable Times (A Port)
Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with
internal conditions such that the output is HIGH except when disabled by the output control. All input pulses have the following characteristics:
frequency
= 10 MHz, t
r = tf = 2 ns, ZO = 50. The outputs are measured one at a time with one transition per measurement.
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參數(shù)描述
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