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參數(shù)資料
| 型號(hào)： | GS9075ACNE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | GS1575A / GS9075A HD-LINX-R II Multi-Rate SDI Automatic Reclocker |
| 中文描述： | GS1575A / GS9075A的HD - LINX進(jìn)程- R的第二多速率SDI自動(dòng)時(shí)鐘恢復(fù)器 |
| 文件頁數(shù)： | 22/29頁 |
| 文件大?。?/td> | 403K |
| 代理商： | GS9075ACNE3 |
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GS1575A / GS9075A Data Sheet
34716 - 0
December 2005
22 of 29
4.10 Lock and LOS
The LOCKED signal is an active high output which indicates when the PLL is
locked.
The internal lock logic of the GS1575A/9075A includes a system which monitors
the Frequency Acquisition Loop and the Phase Acquisition Loop as well as a
monitor to detect harmonic lock.
The LOS (Loss of Signal) output is an active HIGH output which indicates the
absence of data transitions at the DDIx input. In order for this output to be asserted,
transitions must not be present for a period of typically 5.14 us. After this output has
been asserted, LOS will deassert typically 5.14 us after the appearance of a
transition at the DDIx input. This timing relationship is shown in
Figure 4-4
:
Figure 4-4: LOS signal timing
NOTE: LOS is sensitive to transitions appearing at the input, and does not
distinguish between transitions caused by input data, and transitions due to noise.
4.11 Output Drivers and Serial Clock Outputs
The device’s serial digital data outputs (DDO/DDO) have a nominal voltage of
800mv single ended or 1600mV differential when terminated into a 50
Ω
load
.
The GS1575A/9075A may also be configured to output a serial clock at the data
output rate. The internal serial clock output block is powered via the SCO_ENABLE
pin. When SCO_ENABLE is connected to VCC, a differential serial clock output will
be present on SCO/SCO. Otherwise, when SCO_ENABLE is connected to GND,
the clock output block will be powered down and the device will have reduced
power consumption.
NOTE: The SCO_ENABLE signal should have a 1.5mA drive strength to maintain
a supply voltage of 3.3 +/- 0.165V.
Clock and data alignment is shown in
Figure 4-5
.
DATA
LOS
5.14 us
5.14 us
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