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參數(shù)資料
| 型號： | GS9065ACFUE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | GS1535A / GS9065A HD-LINX-R II Multi-Rate SDI Automatic Reclocker |
| 中文描述： | GS1535A / GS9065A的HD - LINX進(jìn)程- R的第二多速率SDI自動時(shí)鐘恢復(fù)器 |
| 文件頁數(shù)： | 19/27頁 |
| 文件大?。?/td> | 345K |
| 代理商： | GS9065ACFUE3 |
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GS1535A / GS9065A Data Sheet
31497 - 3
November 2005
19 of 27
4.4 Frequency Acquisition Loop — The Phase-Frequency Detector
An external crystal of 14.140 MHz is used as a reference to keep the VCO centered
at the last known data rate. This allows the device to achieve a fast synchronous
lock, especially in cases where a known data rate is interrupted. The crystal
reference is also used to clock internal timers and counters. To keep the optimal
performance of the reclocker over all operating conditions, the crystal frequency
must be 14.140 MHz, +/-50ppm. The GO1535 meets this specification and is
available from GENNUM.
The VCO is divided by a selected ratio which is dependant on the input data rate.
The resultant is then compared to the crystal frequency. If the divided VCO
frequency and the crystal frequency are within 1% of each other, the PLL is
considered to be locked to the input data rate.
4.5 Phase Acquisition Loop — The Phase Detector
The phase detector is a digital quadrature phase detector. It indicates whether the
input data is leading or lagging with respect to a clock that is in phase with the VCO
(I-clk) and a quadrature clock (Q-clk). When the phase acquisition loop (PA loop)
is locked, the input data transition is aligned to the falling edge of I-clk and the
output data is re-timed on the rising edge of I-clk. During high input jitter conditions
(>0.25UI), Q-clk will sample a different value than I-clk. In this condition, two extra
phase correction signals will be generated which instructs the charge pump to
create larger frequency corrections for the VCO.
Figure 4-2: Phase Detector Characteristics
When the PA loop is active, the crystal frequency and the incoming data rate are
compared. If the resultant is more that 2%, the PLL is considered to be unlocked
and the system jumps to the FA loop.
i-PHASE ALIGNMENT
EDGE
DATA RE-TIMING
EDGE
q-PHASE ALIGNMENT
EDGE
0.25UI
0.8UI
I-clk
q-clk
INPUT DATA
WITH JITTER
RE-TIMED
OUTPUT DATA
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| GS1559-CBE2 | GS1559 HD-LINX-TM II Multi-Rate Deserializer with Loop-Through Cable Driver |
| GS2905 | 500mA CMOS LDO Voltage Regulator |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS9065BCFUE3 | 功能描述:IC SDI RECLOCKER SMPTE 64LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:電平移位器 應(yīng)用:LCD 電視機(jī)/監(jiān)控器 安裝類型:表面貼裝 封裝/外殼:28-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:28-WQFN（4x4）裸露焊盤 包裝:帶卷 (TR) 其它名稱:296-32523-2TPS65198RUYT-ND |
| GS9065-CFU | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS9065-CFUE3 | 制造商:Semtech Corporation 功能描述:SD/ASI Reclocker |
| GS9068 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:SD SDI Cable Driver |
| GS9068_10 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:SD SDI Cable Driver |
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