- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370391 > GS9064 Telecomm/Datacomm PDF資料下載
參數(shù)資料
| 型號(hào)： | GS9064 |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 39/47頁 |
| 文件大?。?/td> | 754K |
| 代理商： | GS9064 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁當(dāng)前第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁
GENNUM CORPORATION
22208 - 0
39 of 47
G
3.11 PARALLEL DATA OUTPUTS
Data outputs leave the device on the rising edge of PCLK
as shown in Figure 13.
The data may be scrambled or unscrambled, framed or
unframed, and may be presented in 10-bit or 20-bit format.
The output data bus width is controlled independently from
the internal data bus width by the 20bit/10bit input pin.
Likewise, the output data format is defined by the setting of
the external SMPTE_BYPASS and DVB_ASI pins. Recall that
these pins are set by the application layer as inputs to the
device.
3.11.1 Parallel Data Bus Buffers
The parallel data outputs of the GS9060 are driven by high-
impedance buffers which support both LVTTL and LVCMOS
levels. These buffers use a separate power supply of +3.3V
DC supplied via the IO_VDD and IO_GND pins.
All output buffers, including the PCLK output, may be driven
to a high-impedance state if the RESET_TRST signal is
asserted LOW.
Figure 13 PCLK to Data Timing
TABLE 14 HOST INTERFACE DESCRIPTION FOR EDH FLAG REGISTER
REGISTER NAME
BIT
NAME
DESCRIPTION
R/W
DEFAULT
EDH_FLAG
Address: 03h
15
Not Used
14
ANC-UES out
Ancillary Unknown Error Status Flag.
R
0
13
ANC-IDA out
Ancillary Internal device error Detected Already Flag.
R
0
12
ANC-IDH out
Ancillary Internal device error Detected Here Flag.
R
0
11
ANC-EDA out
Ancillary Error Detected Already Flag.
R
0
10
ANC-EDH out
Ancillary Error Detected Here Flag.
R
0
9
FF-UES out
Full Field Unknown Error Status Flag.
R
0
8
FF-IDA out
Full Field Internal device error Detected Already Flag.
R
0
7
FF-IDH out
Full Field Internal device error Detected Here Flag.
R
0
6
FF-EDA out
Full Field Error Detected Already Flag.
R
0
5
FF-EDH out
Full Field Error Detected Here Flag.
R
0
4
AP-UES out
Active Picture Unknown Error Status Flag.
R
0
3
AP-IDA out
Active Picture Internal device error Detected Already Flag.
R
0
2
AP-IDH out
Active Picture Internal device error Detected Here Flag.
R
0
1
AP-EDA out
Active Picture Error Detected Already Flag.
R
0
0
AP-EDH out
Active Picture Error Detected Here Flag.
R
0
PCLK
DOUT[19:0]
DATA
Control signal
output
t
OH
t
OD
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GSA1 | Fuse |
| GSA1.25 | Fuse |
| GSA1.6 | Fuse |
| GSA10 | Fuse |
| GSA750 | Fuse |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS9064A | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GS9064A HD-LINX㈢ II Adaptive Cable Equalizer |
| GS9064ACKDE3 | 制造商:Semtech Corporation 功能描述:Adaptive Cable Equalizer. High-speed BiCMOS integrated circuit. 16-Pin SOIC 制造商:Semtech Corporation 功能描述:SD/ASI Adaptive Equalizer |
| GS9064ACTDE3 | 制造商:Semtech Corporation 功能描述:SD/ASI Adaptive Equalizer |
| GS9064-CKD | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS9064-CKDE3 | 制造商:Gennum Corporation 功能描述:Cable Equalizer 16-Pin SOIC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。