參數(shù)資料
型號(hào)： GS9023-CFY
廠商： Electronic Theatre Controls, Inc.
英文描述： Aluminum Electrolytic Radial Leaded Bi-Polar Capacitor; Capacitance: 100uF; Voltage: 63V; Case Size: 12.5x20 mm; Packaging: Bulk
中文描述： 嵌入式音頻編解碼器
文件頁(yè)數(shù)： 23/33頁(yè)
文件大小： 301K
代理商： GS9023-CFY
GENNUM CORPORATION
522 - 45 - 05
23
G
TABLE 14: Multiplex Mode Host Interface Registers
ADDRESS
BIT
NAME
FUNCTION
R/W
DEFAULT
0h
2-0
VMOD[2:0]
Video standard selection. See Table 1 Valid when
“
VSEL
”
is HIGH. Used in
conjunction with
“
D2_TRS
”
.
“
VMOD[2]
”
is the MSB and
“
VMOD[0]
”
is the
LSB.
R/W
0
3
LOCK
Lock indicator. Same functionality as the LOCK pin. When set HIGH, the
video standard has been identified, the start of a new video frame has been
detected and the device is ready to multiplex audio.
NOTE: LOCK will not be set HIGH unless at least one of the
“
CHACT(4-1)
”
bits (Address #1h) is HIGH.
R
0
4
EDHDEL
EDH data delete. When set LOW, existing EDH packets are removed from the
video stream. When set HIGH, existing EDH packets are passed through
unless overwritten via the EDH_INS pin or the
“
EDHON
”
bit. Valid only when
“
CASCADE
”
(Address #4h bit 7) is LOW.
R/W
0
5
VXST
Video signal detection flag. Set HIGH when the video signal corresponds to
standard selected on the VM[2:0] and TRS pins or with the
“
VMOD[2:0]
”
and
“
D2_TRS
”
bits.
R
0
6
D2_TRS
TRS select. Same functionality as the TRS pin. Used to select video standard
format.When set HIGH, TRS is added to a composite video signal. Valid only
when
“
VSEL
”
is HIGH. Used in conjunction with
“
VMOD[2:0]
”
.
R/W
0
7
VSEL
Video input format (external pin/internal register) configuration select. When
set LOW, the video input format is configured via the VM[2:0] and TRS pins.
When set HIGH, the video input format is configured via the
“
VMOD[2:0]
”
and
“
D2_TRS
”
bits.
R/W
0
1h
3-0
CHACT(4-1)
Audio channel enable. When set HIGH, the corresponding audio channel is
multiplexed into the video signal.
“
CHACT(4)
”
is the MSB and
“
CHACT(1)
”
is
the LSB.
NOTE: Do not rely on default value. Reprogram on power up or reset.
R/W
Fh
4
ACON
Audio Control packet enable. When HIGH, the audio control packet is
multiplexed in the video signal.
R/W
0
5
EDHON
EDH packet enable. Same functionality as the EDH_INS pin. When set HIGH,
the GS9023 performs EDH functions according to SMPTE RP165.
NOTE: Active picture and full field data words are updated from recalculated
values but error flag information is replaced with the values programmed in
Host Interface Registers #Eh and #Fh.
R/W
0
6
A4ON
Extended audio packet enable. Same functionality as the AUXEN pin. When
set HIGH, the extended audio packet is multiplexed in the video signal (24 bit
audio).
R/W
0
7
PKON
Arbitrary data packet enable. When set HIGH, an arbitrary data packet is
multiplexed in the video signal.
R/W
0
2h
7-0
RSV
Not used.
-
3h
3-0
AD20ID[3:0]
Designates the 4 LSBs of the audio data packet DID word. The 6 MSBs are
internally generated.
“
AD20ID[3]
”
is the MSB and
“
AD20ID[0]
”
is the LSB.
R/W
Fh
7-4
AD4ID[3:0]
Designates the 4 LSBs of the extended audio data packet DID word. The 6
MSBs are internally generated.
“
AD4ID[3]
”
is the MSB and
“
AD4ID[0]
”
is the
LSB.
R/W
Eh
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