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參數(shù)資料
| 型號(hào)： | GS9020A |
| 英文描述： | Deserializer with EDH for SDI at 143-540Mb/s and DVB-ASI. |
| 中文描述： | 解串器與硬腦膜外血腫在143 - 540Mb / s和空間數(shù)據(jù)基礎(chǔ)設(shè)施的DVB - ASI。 |
| 文件頁(yè)數(shù)： | 3/30頁(yè) |
| 文件大小： | 445K |
| 代理商： | GS9020A |
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19922 - 2
3
G
AC ELECTRICAL CHARCTERISTICS
V
DD
= 5.0 V, T
A
= 0 - 70
°
C unless otherwise shown.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
Serial Input Clock
Frequency
SCI
-
-
540
MHz
Serial Data Input
Setup Time
t
SS
600
-
-
ps
1
Serial Data Input Hold
Time
t
SH
600
-
-
ps
1
Serial Data Output
Duty Cycle Distortion
-
5
-
%
Serial Output Jitter
540Mb/s at eye crossing
-
360
-
ps p-p
Serial Data Output
Rise Time
-
600
-
ps
Parallel Clock Output
Jitter
27MHz at 50% voltage
level
-
700
-
ps p-p
Input Timing
t
1
20
-
-
ns
2
t
2
-
-
9
ns
2
Output Delay Time
t
OD
with 25pF loading
T/2
-
T/2+7
ns
3
Output Hold Time
t
OH
with 25pF loading
T/2-3
-
-
ns
3
Output Setup Time
t
OS
with 25pF loading
T/2-7
-
-
ns
3
Flag Port Disable Time
t
FDIS
with 25pF loading
-
-
T/2+0.5
ns
Flag Port Enable Time
t
FEN
with 25pF loading
-
-
T/2+1
ns
I
2
C Clock Frequency
SCL
-
-
400
kHz
Host Interface Setup
Time
t
HS
6
-
-
ns
4
Host Interface Hold
Time
t
HH
6
-
-
ns
4
Host Interface Output
Enable Time
t
HEN
with 25pF loading
-
-
21
ns
4
Host Interface Output
Disable Time
t
HDIS
with 25pF loading
-
-
10
ns
4
Reset Time Pulse
Width
t
RESET
100
-
-
ns
NOTES
1. The serial clock rising edge should occur at the centre of the data period for optimum performance. (See Figure 1)
2. Since the GS9020A does not have a parallel clock input, it is not possible to define timing details relative to it. Instead the
GS9020A has a parallel clock output and all timing information is relative to PCLKOUT. The flag port pins (FL[4:0], F_R/W,
S[1:0]) are the only inputs where the timing details are important. The timing requirements are shown in Figure 2.
3. These times are relative to the rising edge of PCLKOUT as shown in Figure 3. Note that the data transitions at the falling
edge of PCLKOUT. T is the parallel clock period in ns.
4. The Host Interface signals, P[7:0], R/W, A/D and CS are asynchronous to the parallel clock.
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