參數資料
型號： GS9015ACPJ
廠商： Electronic Theatre Controls, Inc.
英文描述： Serial Digital Reclocker
中文描述： 串行數字時鐘恢復器
文件頁數： 12/13頁
文件大?。?/td> 138K
代理商： GS9015ACPJ
12
520 - 99 - 05
Application Note - PCB Layout
Special attention must be paid to component layout when designing high performance serial digital receivers. For background
information on high speed circuit and layout design concepts, refer to Document No. 521-32-00, “Optimizing Circuit and Layout
Design of the GS90005A/15A”. A recommended PCB layout can be found in the Gennum Application Note “EB9010B Deserializer
Evaluation Board”
The use of a star grounding technique is required for the loop filter components of the GS9005A/15A.
Controlled impedance PCB traces should be used for the differential clock and data interconnection between the GS9005A and
the GS9000B or GS9000S. These differential traces must not pass over any ground plane discontinuities. A slot antenna is formed
when a microstrip trace runs across a break in the ground plane.
The series resistors at the parallel data output of the GS9000B or GS9000S are used to slow down the fast rise/fall time of the
GS9000B or GS9000S outputs. These resistors should be placed as close as possible to the GS9000B or GS9000S output pins
to minimize radiation from these pins.
(1) To reduce board space, the two anti-series 6.8
μ
F capacitors (connected across pins 2 and 3 of
the GS9010A) may be replaced with a 1.0
μ
F non-polarized capacitor provided that:
(a) the 0.68
μ
F capacitor connected to the OSC pin (11) of the GS9010A is replaced with a
0.33
μ
F capacitor and
(b) the GS9005A /15A Loop Filter Capacitor is 10 nF.
(2) Remove this potentiometer if P/N function is not required, and ground pin 16 of the GS9010A.
(3) The GS9000B will operate to a maximum frequency of 370 Mbps. The GS9000S will operate to
a maximum of 300 Mbps.
Fig. 17 Typical Application Circuit
All resistors in ohms,
all capacitors in microfarads,
all inductors in henries unless otherwise stated.
STANDARD TRUTH TABLE
/2 P/N STANDARD
0 0 4:2:2 - 270
0 1 4:2:2 - 360
1 0 4sc - NTSC
1 1 4sc - PAL
P/N
OUT
IN-
COMP
LF
/2
VCC
SWF
PARALLEL DATA BIT 9
PARALLEL DATA BIT 8
PARALLEL DATA BIT 7
PARALLEL DATA BIT 6
PARALLEL DATA BIT 5
PARALLEL DATA BIT 4
PARALLEL DATA BIT 3
PARALLEL DATA BIT 2
PARALLEL DATA BIT 1
PARALLEL DATA BIT 0
PARALLEL CLOCK OUT
SYNC CORRECTION ENABLE
HSYNC OUTPUT
SYNC WARNING FLAG
STDT
VCC
CD
HSYNC
GND
OSC
DLY
FVCAP
0.1
μ
10
μ
10
μ
+
+
+5V
+5V
100
100
100
100
390
390
390
390
25
24
23
22
21
20
19
5
6
7
8
9
10
11
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
4 3 2 1 28 27 26
V
12 13 14 15 16 17 18
910
5.6p
10n
(1)
(1)
(1)
(2)
0.1
μ
0.1
μ
3.3n
82n
180n
0.68
μ
0.1
μ
0.1
μ
22n
DGND
DGND
DVCC
DGND
DVCC
VCC
DGND
GND
DGND
0.1
μ
SERIAL
1.2k
1.2k
68k
100
100
DVCC
DVCC
DGND
DGND
120
50k
0.1
μ
100k
GS9010A
DD
I
DD
I
VCC1
VEE1
VEE1
/2
VEE3
SDO
SDO
SCO
SCO
SS1
SS0
CD
V
V
V
V
V
V
L
R
R
R
V
R
V
25
24
23
22
21
20
19
5
6
7
8
9
10
11
4 3 2 1 28 27 26
S
0.1
μ
100
100
100
3.3k
100
100
100
100
100
100
100
GS9000B
or GS9000S
PD7
PD6
PD5
PD4
PD3
PD2
PD1
V
V
V
H
P
P
V
V
V
S
S
P
P
STAR
ROUTED
12 13 14 15 16 17 18
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
SWF
VCC
6.8
μ
6.8
μ
+
+
GS9015A
SD
I
SD
I
SC
I
SC
I
SS1
SS0
SST
SWF
(3)
相關PDF資料
PDF描述
GS9015ACTJ Serial Digital Reclocker
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GS9025ACQM Serial Digital Receiver
GS9025ACTM Serial Digital Receiver
GS9028 Cable Driver with Two Adjustable Outputs
相關代理商/技術參數
參數描述
GS9015ACTJ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Serial Digital Reclocker
GS9015B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRANSISTOR | BJT | PNP | 45V V(BR)CEO | 100MA I(C) | TO-92
GS9015B/E6 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRANSISTOR | BJT | PNP | 45V V(BR)CEO | 100MA I(C) | TO-92
GS9015B/E7 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRANSISTOR | BJT | PNP | 45V V(BR)CEO | 100MA I(C) | TO-92
GS9015BCPJ 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述:
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