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參數(shù)資料
| 型號(hào)： | GS9005BCTJ |
| 廠商： | Gennum Corporation |
| 英文描述： | GENLINX-TM GS9005B Serial Digital Receiver |
| 中文描述： | GENLINX -商標(biāo)GS9005B串行數(shù)字接收機(jī) |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大小： | 137K |
| 代理商： | GS9005BCTJ |
10 of 12
32466 - 0
NOTRECOMMENDED
rate, the value of the total R
resistance is approximately
6k8 and for 270 Mb/s operation, the value is approximately
3k5. The 5k potentiometers will then tune the desired data
rate near their mid-points.
FORNEWDESGNS
and 270 MHz respectively) the total resistance required is
approximately the same for both data rates. This also applies
for 177 Mb/s and 360 Mb/s operation (the VCO is tuned
to 354 MHz and 360 MHz respectively). This means that one
potentiometer may be used for each frequency pair with only
a small variation of the fixed resistor value. This halves the
number of adjustments required.
VCO Frequency Setting Resistors
There are two modes of VCO operation available in the
GS9005B. When the /2 ENABLE (pin 10) is LOW, any of the
four VCO frequency setting resistors, RVCO0
through RVCO3
(pins 13, 14, 15 and 17) may be used for any data rate from 100
Jitter performance at the lower data rates (143, 177 Mb/s) is
improved by operating the VCO at twice the normal frequency.
This is accomplished by enabling the /2 function which
activates an additional divide by two block in the PLL section
of the GS9005B.
When the /2 ENABLE is HIGH two of the RVCO pins are
assigned to data rates below 200 Mb/s and two are assigned
to data rates over 200 Mb/s.
The selection is dependent upon the level of the STANDARD
SELECT BIT, SS1 (pin 21). When SS1 is LOW, RVCO0
and
RVCO1 (pins 13 and 14) are used for the higher data rates.
When SS1 is HIGH, the VCO frequency is now twice the bit rate
and its frequency is set by RVCO2 and RVCO3 (pins 15 and
17).
For 143 Mb/s and 270 Mb/s operation, (the VCO is at 286 MHz
Fig. 15 GS9005B Typical Test Circuit Using -5V Supply
All resistors in ohms, all capacitors in microfarads, all inductors in henries unless otherwise stated.
10μ
ECL
DATA
INPUTS
0.1μ
DATA
DATA
CLOCK
100
100
100
100
390
390
390
390
0.1μ
+
0.1μ
25
24
23
22
21
20
19
5
6
7
8
9
10
11
4 3 2 1 28 27 26
V
12 13 14 15 16 17 18
910
22n
75
113
75
47p
-5V
-5V
-5V
÷1
÷2
0.1μ
47p
0.1μ
-5V
10k
CARRIER
DETECT
OUTPUT
INPUT
GS9005B
DD
I
DD
I
VCC2
SD
I
SD
I
/2
VEE3
SDO
SDO
SCO
SCO
SS1
SS0
CD
V
A
A
S
I
V
V
L
V
SSI
LOOP
VOLTAGE
See Figure 18
ANALOG
DIGITAL
5.6p
-5V
-5V
-5V
-5V
-5V
10n
STAR
ROUTED
CLOCK
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