參數資料
型號: GS9002ACPM
廠商: Gennum Corporation
英文描述: GENLINX-TM GS9002A Serial Digital Encoder
中文描述: GENLINX -商標GS9002A串行數字編碼器
文件頁數: 5/11頁
文件大小: 456K
代理商: GS9002ACPM
5 of 11
24149 - 1
N
GS9002A PIN DESCRIPTIONS
PIN NO.
SYMBOL TYPE
DESCRIPTION
1
V
EE
Power Supply: Most negative power supply connection.
2
V
CC3
Power Supply: Most positive power supply connection for the PLL and scrambler.
3
SYNC DET.
O
TTL output level that detects the occurrence of all zero’s or all one’s at inputs PD2-PD9
and pulses LOW for three PCK-IN durations. Used to detect SMPTE 259M reserved words
(000-003 and 3FC-3FF) in TRS sync word. Parallel data bits PD0 and PD1 are set Low or
High when PD2 - PD9 are Low or High respectively.
4
V
EE
Power Supply: Most negative power supply connection.
5
V
CC1
Power Supply: Most positive power supply connection for the input data latches and serializer.
6
SYNC DET.
DISABLE
I
TTL level input that disables the internal Sync Detector when HIGH. This allows the
GS9002 to serialize 8 or 10 bit non - SMPTE Standard parallel data.
7-16
PD0-PD9
I
TTL level inputs of the parallel data words. PD0 is the LSB and PD9 is the MSB.
17
PCK-IN
I
TTL level input of the Parallel Clock.
18
V
EE
Power Supply: Most negative power supply connection.
19
PCK OUT
O
Pseudo-ECL output representing the re-clocked Parallel Clock and is derived from the
internal VCO. The VCO is divided by 10 in order to produce this output.
20
LOCK DET.
O
TTL level output which goes HIGH when the internal PLL is locked.
21
V
CC3
Power Supply: Most positive power supply connection for the PLL and scrambler.
22
LOOP FILT.
I
Connection for the R-C loop filter components. The loop filter sets the PLL loop
parameters.
23
V
EE
Power Supply: Most negative power supply connection.
24
NC
25
V
EE
Power Supply: Most negative power supply connection.
26
SSS
I
Scrambler/Serializer Select. TTL level input that selects scrambled NZRI output when
logic LOW or direct serializer output when logic HIGH.
27
V
EE
Power Supply: Most negative power supply connection.
28
V
CC3
Power Supply: Most positive power supply connection for the PLL and scrambler.
29
C
REG
I
Compensation RC network for internal voltage regulator that requires decoupling with a series
0.1μF capacitor and
820
resistor. Components should be located as close as possible to the pin.
30
V
EE
Power Supply: Most negative power supply connection.
31
R
VCO3
I
VCO Resistor 3: Analog current input used to set the centre frequency of the VCO when
the two Data Rate Select bits (pins 35 and 36) are both set to logic 1. A resistor is
connected from this pin to V
EE
.
32
R
VCO2
I
VCO Resistor 2: Analog current input used to set the centre frequency of the VCO when
the Data Rate Select Bit 0 (pin 36) is set to logic 0 and the Data Rate Select Bit 1 (pin 35)
is set to logic 1. A resistor is connected from this pin to V
EE
.
33
R
VCO1
I
VCO Resistor 1: Analog current input used to set the centre frequency of the VCO when
the Data Rate Select Bit 0 (pin 36) is set to logic 1 and the Data Rate Select Bit 1 (pin 35)
is set to logic 0. A resistor is connected from this pin to V
EE
.
34
R
VCO0
I
VCO Resistor 0: Analog current input used to set the centre frequency of the VCO when
the two Data Rate Select bits (pins 35 and 36) are both set to logic 0. A resistor is
connected from this pin to V
EE
.
35,36
DRS0, 1
I
TTL level inputs to the internal 2:4 demultiplexer used to select one of four VCO frequency
setting resistors (R
VCO0
- R
VCO3
). (See above)
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