參數(shù)資料
型號(hào): GS90015BCPJE3
廠商: Gennum Corporation
英文描述: GENLINX-TM GS9015B Serial Digital Reclocker
中文描述: GENLINX -商標(biāo)GS9015B串行數(shù)字時(shí)鐘恢復(fù)器
文件頁數(shù): 12/13頁
文件大?。?/td> 119K
代理商: GS90015BCPJE3
12 of 13
NOTRECOMMENDED
FORNEWDESGNS
all inductors in henries unless otherwise stated.
32467 - 0
Application Note - PCB Layout
Special attention must be paid to component layout when designing high performance serial digital receivers. For background
information on high speed circuit and layout design concepts, refer to Document No. 521-32-00, “Optimizing Circuit and Layout
Design of the GS90005A/15A”. A recommended PCB layout can be found in the Gennum Application Note “EB9010B
Deserializer Evaluation Board”
The use of a star grounding technique is required for the loop filter components of the GS9005B/15B.
Controlled impedance PCB traces should be used for the differential clock and data interconnection between the GS9005B
and the GS9000B or GS9000S. These differential traces must not pass over any ground plane discontinuities. A slot antenna
is formed when a microstrip trace runs across a break in the ground plane.
The series resistors at the parallel data output of the GS9000B or GS9000S are used to slow down the fast rise/fall time of the
GS9000B or GS9000S outputs. These resistors should be placed as close as possible to the GS9000B or GS9000S output pins
to minimize radiation from these pins.
(1) To reduce board space, the two anti-series 6.8 μF capacitors (connected across pins 2 and 3 of
the GS9010A) may be replaced with a 1.0 μF non-polarized capacitor provided that:
(a) the 0.68 μF capacitor connected to the OSC pin (11) of the GS9010A is replaced with a
0.33 μF capacitor and
(b) the GS9005B /15B Loop Filter Capacitor is 10 nF.
(2) Remove this potentiometer if P/N function is not required, and ground pin 16 of the GS9010A.
(3) The GS9000B will operate to a maximum frequency of 370 Mbps. The GS9000S will operate to
a maximum of 300 Mbps.
Fig. 16 Typical Application Circuit
All resistors in ohms,
all capacitors in microfarads,
STANDARD TRUTH TABLE
/2 P/N STANDARD
0 1 4:2:2 - 360
1 0 4sc - NTSC
1 1 4sc - PAL
P/N
OUT
IN-
COMP
LF
/2
VCC
SWF
PARALLEL DATA BIT 9
PARALLEL DATA BIT 8
PARALLEL DATA BIT 7
PARALLEL DATA BIT 6
PARALLEL DATA BIT 5
PARALLEL DATA BIT 4
PARALLEL DATA BIT 3
PARALLEL DATA BIT 2
PARALLEL DATA BIT 1
PARALLEL DATA BIT 0
PARALLEL CLOCK OUT
SYNC CORRECTION ENABLE
HSYNC OUTPUT
SYNC WARNING FLAG
STDT
VCC
CD
HSYNC
GND
OSC
DLY
FVCAP
0.1μ
10μ
10μ
+
+
+5V
+5V
100
100
100
100
390
390
390
390
25
24
23
22
21
20
19
5
6
7
8
9
10
11
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
4 3 2 1 28 27 26
V
12 13 14 15 16 17 18
910
5.6p
10n
(1)
(1)
(2)
0.1μ
0.1μ
3.3n
82n
180n
0.68μ
0.1μ
0.1μ
22n
DGND
DGND
DVCC
DGND
DVCC
VCC
DGND
GND
DGND
0.1μ
SERIAL
DIGITAL
INPUT
1.2k
1.2k
68k
100
100
DVCC
DVCC
DGND
DGND
120
50k
0.1μ
100k
GS9010A
DD
I
DD
I
VCC1
VEE1
VEE1
/2
VEE3
SDO
SDO
SCO
SCO
SS1
SS0
CD
V
V
V
V
V
V
L
V
V
25
24
23
22
21
20
19
5
6
7
8
9
10
11
4 3 2 1 28 27 26
S
0.1μ
100
100
100
3.3k
100
100
100
100
100
100
100
GS9000B
or GS9000S
PD7
PD6
PD5
PD4
PD3
PD2
PD1
V
V
V
H
P
P
V
V
V
S
S
P
P
STAR
ROUTED
12 13 14 15 16 17 18
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
SWF
VCC
6.8μ
6.8μ
+
+
GS9015B
SD
I
SD
I
SC
I
SC
I
SS1
SS0
SST
SWF
(3)
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