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參數(shù)資料
| 型號： | GS9000DCTJE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | GENLINX II -TM GS9000D Serial Digital Decoder |
| 中文描述： | GENLINX二，商標(biāo)GS9000D串行數(shù)字解碼器 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大小： | 118K |
| 代理商： | GS9000DCTJE3 |
GENNUM CORPORATION
18784 - 3
5 of 9
G
INPUT/OUTPUT CIRCUITS
Fig. 2 Pin 11 SSC
Fig. 3 Pin 14 SCE
Fig. 4 Pins 5 - 8 SDI - SCI
15
SWC
Input
Sync Warning Control
. Analog input used to set the HSYNC Error Rate (HER). This is
accomplished by an external RC time constant connected to this pin.
16
PCLK
Output
Parallel Clock Output.
CMOS (TTL compatible) clock output where the rising edge of the
clock is located at the centre of the parallel data window within a given tolerance. See Fig. 7.
17
PD0
Output
Parallel Data Output - Bit 0 (LSB)
. CMOS (TTL compatible) descrambled parallel data output
from the serial to parallel convertor representing the least significant bit (LSB).
18
V
DD
Power Supply.
Most positive power supply connection.
19-25
PD1 - PD7
Outputs
Parallel Data Outputs - Bit 1 to Bit 7.
CMOS (TTL compatible) descrambled parallel data
outputs from the serial to parallel convertor representing data bit 1 through data bit 7.
26
V
SS
Power Supply
. Most negative power supply connection.
27
PD8
Output
Parallel Data Output.
CMOS (TTL compatible) descrambled parallel data output from the
serial to parallel convertor representing data bit 8.
28
PD9
Output
Parallel Data Output - Bit 9 (MSB)
. CMOS (TTL compatible) descrambled data output from
the serial to parallel convertor representing the most significant bit (MSB).
PIN DESCRIPTIONS
PIN NO.
SYMBOL
TYPE
DESCRIPTION
R
EXT
EXTERNAL
COMPONENTS
SSC
V
DD
V
DD
SCE
V
DD
V
DD
SDI
SCI
BIAS
SDI
SCI
V
DD
V
DD
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相關(guān)代理商/技術(shù)參數(shù) |
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| GS9000S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Serial Digital Decoder |
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| GS9000SCTJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| GS9001 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EDH COPROCESSOR |
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