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參數(shù)資料
| 型號(hào)： | GS9000DCTJ |
| 廠商： | Gennum Corporation |
| 英文描述： | GENLINX II -TM GS9000D Serial Digital Decoder |
| 中文描述： | GENLINX二，商標(biāo)GS9000D串行數(shù)字解碼器 |
| 文件頁(yè)數(shù)： | 7/9頁(yè) |
| 文件大?。?/td> | 118K |
| 代理商： | GS9000DCTJ |
GENNUM CORPORATION
18784 - 3
7 of 9
G
Fig. 8 GS9000D Test Set-Up
With synchronized serial data and clock connected to the
GS9000D, the HSYNC output (pin 1) will toggle for each
HSYNC detected. The Parallel Data bits PD0 through PD9
and the Parallel Clock can be observed on an oscilloscope
or fed to a logic analyzer. To directly drive parallel inputs to
receiving equipment, such as monitors or digital to analog
converters, these outputs can be fed through a suitable TTL
to ECL converter.
In operation, the HSYNC output from the GS9000D decoder
toggles on each occurrence of the timing reference signal
(TRS). The state of the HSYNC output is not significant, but
the time at which it toggles is significant.
Fig. 9 Operation of HSYNC Output
The HSYNC output toggles to indicate the presence of the
TRS on the falling edge of PCLK, one data symbol prior to
the output of the first word in the TRS. In the following
diagram, data is indicated in 10-bit Hex.
Fig. 10 Operation of HSYNC with Respect to PCLK
DECODER
GS9000D
1
4
3
6
5
7
SDI
SDI
SCI
SCI
SS1
SS0
SSC
9
8
10
2
PARALLEL DATA BIT 0
PARALLEL DATA BIT 1
PARALLEL DATA BIT 2
PARALLEL DATA BIT 3
PARALLEL DATA BIT 4
PARALLEL DATA BIT 5
PARALLEL DATA BIT 6
PARALLEL DATA BIT 7
PARALLEL DATA BIT 8
PARALLEL DATA BIT 9
PARALLEL CLOCK OUT
SYNC CORRECTION ENABLE
HSYNC OUTPUT
STANDARDS SELECT BIT 1
STANDARDS SELECT BIT 0
3 x 100n
**
17
18
19
20
15
16
14
12
V
DD
V
DD
V
DD
HSYNC
13
11
+5V
PD0
PDI
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PCLK
SCE
V
SS
V
SS
V
SS
SWC SWF
26
21
22
23
24
25
27
28
10p
+5V
** Locate the three 0.10μF decoupling
capacitors as close as possible to the
corresponding pins on the GS9000D.
Chip capacitors are recommended.
SYNC WARNING FLAG
SDI
IN
SDI
IN
SCI
IN
SCI
IN
39k
13 x 425
+5V
100k
820p
22μ
All resistors in ohms,
all capacitors in farads,
unless otherwise specified.
T
R
S
T
R
S
T
R
S
ACTIVE VIDEO
& H BLANKING
ACTIVE VIDEO
& H BLANKING
E
A
V
H
BLNK
S
A
V
ACTIVE
VIDEO
E
A
V
H
BLNK
S
A
V
4
DATA
STREAM
HSYNC
OUT
4:2:2
DATA
STREAM
HSYNC
OUT
XXX 3FF 000 000 XXX
XXX 3FF 000 000 XXX
PCLK
PDN
HSYNC
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