參數(shù)資料
型號: GS9000DCPJ
廠商: Gennum Corporation
英文描述: GENLINX II -TM GS9000D Serial Digital Decoder
中文描述: GENLINX二,商標(biāo)GS9000D串行數(shù)字解碼器
文件頁數(shù): 6/9頁
文件大?。?/td> 118K
代理商: GS9000DCPJ
GENNUM CORPORATION
18784 - 3
6 of 9
G
Fig. 5 Pin 15 SWC
Fig. 6 Pins 3, 16, 17, 19 - 25, 27, 28
SWF, HSYNC, SSI, SSD, PCLK, PD0-9
Fig. 7 Waveforms
TEST SET-UP & APPLICATION INFORMATION
Figure 8 shows the test set-up for the GS9000D operating
from a V
DD
supply of +5 volts. The differential pseudo ECL
inputs for DATA and CLOCK (pins 5,6,7 and 8) must be
biased between +3.0 and +4.05 volts.
In the application
circuit shown in Figure 11, these inputs can be directly
driven from the outputs of the GS7025 Reclocking Receiver
with their resistor values set as shown.
In other cases, such as true ECL level driver outputs, two
biasing resistors are needed on the DATA and CLOCK
inputs and the signals must be AC coupled.
It is critical that the decoupling capacitors connected to
pins 12,13 and 18 are chip types and are located as close
as possible to the device pins.
The critical high speed inputs, such as Serial Data
(pins 5 and 6) and Serial Clock (pins 7 and 8), are located
along one side of the device package to maintain very short
interconnections when interfacing with the GS7025
Receiver.
If the automatic standard select function is not used, the
Standard Select bits (pins 9 and 10) do not need to be
connected, however the control input (pin 11) should be
grounded.
R
EXT
C
EXT
SWC
EXTERNAL
COMPONENTS
V
DD
V
DD
6k8
GND
OUTPUT
V
DD
t
SU
t
HOLD
t
CLKL
=
t
CLKH
SERIAL
CLOCK
(SCI)
SERIAL
DATA
(SDI)
50%
PARALLEL
DATA
(PDn)
50%
PARALLEL
CLOCK
(PCLK)
1/2
T
1/2
T
t
D
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS9000DCPJE3 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GENLINX II -TM GS9000D Serial Digital Decoder
GS9000DCTJ 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GENLINX II -TM GS9000D Serial Digital Decoder
GS9000DCTJE3 制造商:Gennum Corporation 功能描述:
GS9000S 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Serial Digital Decoder
GS9000SCPJ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SMPTE