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參數(shù)資料
| 型號： | GS9000CCTJ |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Serial Digital Decoder |
| 中文描述： | 串行數(shù)字解碼器 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大小： | 106K |
| 代理商： | GS9000CCTJ |
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G
DECODER
GS9000C
1
4
3
6
5
7
SDI
SDI
SCI
SCI
SS1
SS0
SSC
9
8
10
2
PARALLEL DATA BIT 0
PARALLEL DATA BIT 1
PARALLEL DATA BIT 2
PARALLEL DATA BIT 3
PARALLEL DATA BIT 4
PARALLEL DATA BIT 5
PARALLEL DATA BIT 6
PARALLEL DATA BIT 7
PARALLEL DATA BIT 8
PARALLEL DATA BIT 9
PARALLEL CLOCK OUT
SYNC CORRECTION ENABLE
HSYNC OUTPUT
STANDARDS SELECT BIT 1
STANDARDS SELECT BIT 0
3 x 100n
**
17
18
19
20
15
16
14
12
13
11
+5V
PD0
PDI
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PCLK
SCE
V
SS
V
SS
V
SS
SWC SWF
26
V
DD
V
DD
V
DD
HSYNC
21
22
23
24
25
27
28
10p
+5V
** Locate the three 0.10
μ
F decoupling
capacitors as close as possible to the
corresponding pins on the GS9000C.
Chip capacitors are recommended.
SYNC WARNING FLAG
SDI
IN
SDI
IN
SCI
IN
SCI
IN
39k
13 x 425
+5V
100k
820p
22
μ
All resistors in ohms,
all capacitors in farads,
unless otherwise specified.
Fig. 8 GS9000C Test Set-Up
With correctly synchronized serial data and clock connected
to the GS9000C, the HSYNC output (pin 1) will toggle for each
HSYNC detected. The Parallel Data bits PD0 through PD9
along with the Parallel Clock can be observed on an
oscilloscope or fed to a logic analyzer. These outputs can
also be fed through a suitable TTL to ECL converter to directly
drive parallel inputs to receiving equipment such as monitors
or digital to analog converters.
In operation, the HSYNC output from the GS9000C decoder
toggles on each occurrence of the timing reference signal
(TRS). The state of the HSYNC output is not significant, just
the time at which it toggles.
The HSYNC output toggles to indicate the presence of the
TRS on the falling edge of PCLK, one data symbol prior to the
output of the first word in the TRS. In the following diagram,
data is indicated in 10 bit Hex.
T
R
S
T
R
S
T
R
S
ACTIVE VIDEO
& H BLANKING
ACTIVE VIDEO
& H BLANKING
E
A
V
H
BLNK
S
A
V
ACTIVE
VIDEO
E
A
V
H
BLNK
S
A
V
4
SC
DATA
STREAM
HSYNC
OUT
4:2:2
DATA
STREAM
HSYNC
OUT
Fig. 9 Operation of HSYNC Output
XXX 3FF 000 000 XXX
XXX 3FF 000 000 XXX
PCLK
PDN
HSYNC
Fig. 10 Operation of HSYNC with Respect to PCLK
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| GS9000-CPJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SMPTE |
| GS9000CPTJE3 | 制造商:Gennum Corporation 功能描述: |
| GS9000D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:270Mb/s Deserializer for use with GS7025. GS9025A or GS9035A. |
| GS9000DCPJ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS9000DCPJE3 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GENLINX II -TM GS9000D Serial Digital Decoder |
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