- 您現(xiàn)在的位置：買賣IC網 > PDF目錄383055 > GS882Z36B-100 (Electronic Theatre Controls, Inc.) 8Mb Pipelined and Flow Through Synchronous NBT SRAMs PDF資料下載
參數(shù)資料
| 型號： | GS882Z36B-100 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8Mb Pipelined and Flow Through Synchronous NBT SRAMs |
| 中文描述： | 8MB的流水線和流量，通過同步唑靜態(tài)存儲器 |
| 文件頁數(shù)： | 24/34頁 |
| 文件大小： | 802K |
| 代理商： | GS882Z36B-100 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁
Rev: 1.15 6/2001
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
24/34
1998, Giga Semiconductor, Inc.
Preliminary
.
GS882Z18/36B-11/100/80/66
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner consistent with IEEE Standard 1149.1-1990, a serial boundary scan interface
standard (commonly referred to as JTAG), but does not implement all of the functions required for 1149.1 compliance. Some
functions have been modified or eliminated because they can slow the RAM. Nevertheless, the RAM supports 1149.1-1990 TAP
(Test Access Port) Controller architecture, and can be expected to function in a manner that does not conflict with the operation of
Standard 1149.1 compliant devices. The JTAG Port interfaces with conventional TTL / CMOS logic level signaling.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits. To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either V
DD
or V
SS
. TDO should be left unconnected.
JTAG Port Registers
Overview
The various JTAG registers, refered to as TAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS
as TCK is strobed. Each of the TAP Registers are serial shift registers that capture serial input data on the rising edge of TCK and
push serial data out on the next falling edge of TCK. When a register is selected it is placed between the TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single-bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAMs JTAG Port to another device in the scan chain with as little delay as possible.
JTAG Pin Descriptions
Pin
Pin Name
I/O
Description
TCK
Test Clock
In
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the
falling edge of TCK.
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state
machine. An undriven TMS input will produce the same result as a logic one input level.
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed
between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP
Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to
the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input
level.
Output that is active depending on the state of the TAP state machine. Output changes in response to the
falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO.
TMS
Test Mode
Select
In
TDI
Test Data In
In
TDO
Test Data Out
Out
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
相關PDF資料 |
PDF描述 |
|---|---|
| GS882Z36B-100I | 8Mb Pipelined and Flow Through Synchronous NBT SRAMs |
| GS882Z36B-11 | 8Mb Pipelined and Flow Through Synchronous NBT SRAMs |
| GS882Z36B-11I | 8Mb Pipelined and Flow Through Synchronous NBT SRAMs |
| GS882Z36B-66 | 8Mb Pipelined and Flow Through Synchronous NBT SRAMs |
| GS882Z36B-66I | 8Mb Pipelined and Flow Through Synchronous NBT SRAMs |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| GS882Z36BD-250I V | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V/2.5V 9MBIT 256KX36 5.5NS/3NS 165FPBGA - Trays |
| GS882Z36CB-200V | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 1.8V/2.5V 9MBIT 256KX36 6.5NS/3NS 119FPBGA - Trays |
| GS882Z36CB-250V | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 1.8V/2.5V 9MBIT 256KX36 5.5NS/3NS 119FPBGA - Trays |
| GS882Z36CB-300 | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 2.5V/3.3V 9MBIT 256KX36 5NS/2.5NS 119FPBGA - Trays |
| GS882Z36CD-200I | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 2.5V/3.3V 9MBIT 256KX36 6.5NS/3NS 165FPBGA - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復。