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參數(shù)資料
| 型號： | GS882Z18B-66 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8Mb Pipelined and Flow Through Synchronous NBT SRAMs |
| 中文描述： | 8MB的流水線和流量，通過同步唑靜態(tài)存儲器 |
| 文件頁數(shù)： | 4/34頁 |
| 文件大小： | 802K |
| 代理商： | GS882Z18B-66 |
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Rev: 1.15 6/2001
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
4/34
1998, Giga Semiconductor, Inc.
Preliminary
.
GS882Z18/36B-11/100/80/66
GS882Z18/36 BGA Pin Description
Pin Location
P4, N4
Symbol
A
0
, A
1
Type
I
Description
Address field LSBs and Address Counter Preset Inputs
A2, A3, A5, A6, B3, B5, C2, C3, C5,
C6, G4, R2, R6, T3, T5
T4
T2, T6
T2, T6
K7, L7, N7, P7, K6, L6, M6, N6, P6
H7, G7, E7, D7, H6, G6, F6, E6, D6
H1, G1, E1, D1, H2, G2, F2, E2, D2
K1, L1, N1, P1, K2, L2, M2, N2, P2
L5, G5, G3, L3
P7, N6, L6, K7, H6, G7, F6, E7, D6
D1, E2, G2, H1, K2, L1, M2, N1, P2
L5, G3
P6, N7, M6, L7, K6, H7, G6, E6, D7,
D2, E1, F2, G1, H2, K1, L2, N2, P1,
G5, L3, T4
K4
M4
H4
E4
B2
B6
F4
B4
T7
R5
R3
R7
J3
J5
An
I
Address Inputs
An
NC
An
I
Address Inputs (x36 Version)
No Connect (x36 Version)
Address Inputs (x18 Version)
—
I
DQ
A1
–DQ
PA9
DQ
B1
–DQ
PB9
DQ
C1
–DQ
PC9
DQ
D1
–DQ
PD9
B
A
, B
B
, B
C
, B
D
DQ
A1
–DQ
A9
DQ
B1
–DQ
B9
B
A
, B
B
I/O
Data Input and Output pins (x36 Version)
I
Byte Write Enable for DQ
A
, DQ
B
, DQ
C
, DQ
D
I/Os; active low ( x36 Version)
I/O
Data Input and Output pins (x18 Version)
I
Byte Write Enable for DQ
A
, DQ
B
Data I/Os; active low ( x18 Version)
NC
—
No Connect (x18 Version)
CK
CKE
W
E
1
E
2
E
3
G
ADV
ZZ
FT
LBO
PE
DP
QE
I
I
I
I
I
I
I
I
I
I
I
I
I
Clock Input Signal; active high
Clock Input Buffer Enable; active low
Write Enable—Writes all enabled bytes; active low
Chip Enable; active low
Chip Enable; active high
Chip Enable; active low
Output Enable; active low
Burst address counter advance enable; active high
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode)
Data Parity Mode Input; 1 = Even, 0 = Odd
Parity Error Out; Open Drain Output
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
No Connect
O
D4
ZQ
I
B1, C1, R1, T1, L4, B7, C7, U6
NC
—
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