參數(shù)資料
型號(hào)： GS882Z18B-100
廠商： Electronic Theatre Controls, Inc.
英文描述： 8Mb Pipelined and Flow Through Synchronous NBT SRAMs
中文描述： 8MB的流水線和流量，通過(guò)同步唑靜態(tài)存儲(chǔ)器
文件頁(yè)數(shù)： 28/34頁(yè)
文件大小： 802K
代理商： GS882Z18B-100
Rev: 1.15 6/2001
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
28/34
1998, Giga Semiconductor, Inc.
Preliminary
.
GS882Z18/36B-11/100/80/66
JTAG TAP Instruction Set Summary
JTAG Port Recommended Operating Conditions and DC Characteristics
Instruction
Code
Description
Notes
EXTEST
000
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
This RAM does not implement 1149.1 EXTEST function. *Not 1149.1 Compliant *
Preloads ID Register and places it between TDI and TDO.
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
Forces all RAM output drivers to High-Z.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
This RAM does not implement 1149.1 PRELOAD function. *Not 1149.1 Compliant *
GSI private instruction.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
Places Bypass Register between TDI and TDO.
1
IDCODE
001
1, 2
SAMPLE-Z
010
1
RFU
011
1
SAMPLE/
PRELOAD
GSI
100
1
101
1
RFU
110
1
BYPASS
111
1
Notes:
1.
2.
Instruction codes expressed in binary, MSB on left, LSB on right.
Default instruction automatically loaded at power-up and in test-logic-reset state.
Parameter
Symbol
V
IHT
V
ILT
I
INTH
I
INTL
I
OLT
V
OHT
V
OLT
Min.
Max.
V
DD
+0.3
Unit Notes
Test Port Input High Voltage
1.7
V
1, 2
Test Port Input Low Voltage
–0.3
0.8
V
1, 2
TMS, TCK and TDI Input Leakage Current
–300
1
uA
3
TMS, TCK and TDI Input Leakage Current
–1
1
uA
4
TDO Output Leakage Current
–1
1
uA
5
Test Port Output High Voltage
2.4
—
V
6, 7
Test Port Output Low Voltage
—
0.4
V
6, 8
Notes:
1.
2.
This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.
Input Under/overshoot voltage must be –2 V > Vi < V
DD
+2 V with a pulse width not to exceed 20%
tTKC.
V
DD
≥
V
IN
≥
V
IL
0 V
≤
V
IN
≤
V
IL
Output Disable, V
OUT
= 0 to V
DD
The TDO output driver is served by the V
DD
supply.
I
OH
= –4 mA
I
OL
= +4 mA
3.
4.
5.
6.
7.
8.
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