參數(shù)資料
型號(hào): GS882V37AB-225
廠商: GSI TECHNOLOGY
元件分類(lèi): DRAM
英文描述: 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
中文描述: 256K X 36 CACHE SRAM, 2.2 ns, PBGA119
封裝: PLASTIC, BGA-119
文件頁(yè)數(shù): 7/28頁(yè)
文件大?。?/td> 637K
代理商: GS882V37AB-225
GS882V37AB/D-250/225/200
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 7/2004
7/28
2002, GSI Technology
Mode Pin Functions
Note:
There is a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the
above tables.
Burst Counter Sequences
BPR 1999.05.18
Mode Name
Pin
Name
State
Function
Burst Order Control
LBO
L
H
Linear Burst
Interleaved Burst
Active
Standby, I
DD
= I
SB
Dual Cycle Deselect
Single Cycle Deselect
High Drive (Low Impedance)
Low Drive (High Impedance)
Activate DQPx I/Os (x18/x36
mode)
Deactivate DQPx I/Os (x16/x32
mode)
Power Down Control
ZZ
L or NC
H
Single/Dual Cycle Deselect Control
SCD
L
H or NC
L
H or NC
FLXDrive Output Impedance Control
ZQ
9th Bit Enable
PE
L
H or NC
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
相關(guān)PDF資料
PDF描述
GS882V37AB-225I 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
GS882V37AB-250 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
GS882V37AB-250I 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
GS882V37AD-200 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
GS882V37AD-200I 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
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