參數(shù)資料
型號(hào): GS882V36BGD-300I
廠商: GSI TECHNOLOGY
元件分類: DRAM
英文描述: 512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
中文描述: 256K X 36 CACHE SRAM, 5 ns, PBGA165
封裝: 13 X 15 MM, 1 MM PITCH, LEAD FREE, FBGA-165
文件頁(yè)數(shù): 18/36頁(yè)
文件大?。?/td> 732K
代理商: GS882V36BGD-300I
GS882V18/36BB/D-333/300/250/200
Rev: 1.02 3/2005
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
18/36
2004, GSI Technology
Notes:
1.
2.
These parameters are sampled and are not 100% tested.
ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
AC Electrical Characteristics
Parameter
Symbol
-333
-300
-250
-200
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Pipeline
Clock Cycle Time
tKC
3.0
3.3
4.0
5.0
ns
Clock to Output Valid
tKQ
2.5
2.5
2.5
3.0
ns
Clock to Output Invalid
tKQX
1.5
1.5
1.5
1.5
ns
Clock to Output in Low-Z
tLZ
1
1.5
1.5
1.5
1.5
ns
Setup time
tS
1.0
1.0
1.2
1.4
ns
Hold time
tH
0.1
0.1
0.2
0.4
ns
Flow
Through
Clock Cycle Time
tKC
4.5
5.0
5.5
6.5
ns
Clock to Output Valid
tKQ
4.5
5.0
5.5
6.5
ns
Clock to Output Invalid
tKQX
2.0
2.0
2.0
2.0
ns
Clock to Output in Low-Z
tLZ
1
2.0
2.0
2.0
2.0
ns
Setup time
tS
1.3
1.4
1.5
1.5
ns
Hold time
tH
0.3
0.4
0.5
0.5
ns
Clock HIGH Time
tKH
1.0
1.0
1.3
1.3
ns
Clock LOW Time
tKL
1.2
1.2
1.5
1.5
ns
Clock to Output in
High-Z
tHZ
1
1.5
2.5
1.5
2.5
1.5
2.5
1.5
3.0
ns
G to Output Valid
tOE
2.5
2.5
2.5
3.0
ns
G to output in Low-Z
tOLZ
1
0
0
0
0
ns
G to output in High-Z
tOHZ
1
2.5
2.5
2.5
3.0
ns
ZZ setup time
tZZS
2
5
5
5
5
ns
ZZ hold time
tZZH
2
1
1
1
1
ns
ZZ recovery
tZZR
20
20
20
20
ns
相關(guān)PDF資料
PDF描述
GS882V36BGD-333 512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
GS882V36BGD-333I 512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
GS882V37AB-225 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
GS882V37AB-225I 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
GS882V37AB-250 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
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