參數(shù)資料
型號: GS882V36BGD-250
廠商: GSI TECHNOLOGY
元件分類: DRAM
英文描述: 512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
中文描述: 256K X 36 CACHE SRAM, 5.5 ns, PBGA165
封裝: 13 X 15 MM, 1 MM PITCH, LEAD FREE, FBGA-165
文件頁數(shù): 28/36頁
文件大?。?/td> 732K
代理商: GS882V36BGD-250
GS882V18/36BB/D-333/300/250/200
Rev: 1.02 3/2005
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
28/36
2004, GSI Technology
JTAG TAP Instruction Set Summary
Instruction
Code
Description
Notes
EXTEST
000
Places the Boundary Scan Register between TDI and TDO.
1
IDCODE
001
Preloads ID Register and places it between TDI and TDO.
1, 2
SAMPLE-Z
010
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Forces all RAM output drivers to High-Z.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
RFU
011
1
SAMPLE/
PRELOAD
100
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
1
GSI
101
GSI private instruction.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
RFU
110
1
BYPASS
111
Places Bypass Register between TDI and TDO.
1
Notes:
1.
2.
Instruction codes expressed in binary, MSB on left, LSB on right.
Default instruction automatically loaded at power-up and in test-logic-reset state.
相關(guān)PDF資料
PDF描述
GS882V36BGD-250I 512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
GS882V36BGD-300 512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
GS882V36BGD-300I 512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
GS882V36BGD-333 512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
GS882V36BGD-333I 512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
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