參數(shù)資料
型號: GS88218BB-300
廠商: Electronic Theatre Controls, Inc.
英文描述: 512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
中文描述: 為512k × 18,256K × 36 9Mb以上SCD的/雙氰胺同步突發(fā)靜態(tài)存儲器
文件頁數(shù): 6/37頁
文件大?。?/td> 751K
代理商: GS88218BB-300
GS88218/36BB/D-333/300/250/200/150
Rev: 1.02 10/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
6/37
2002, GSI Technology
GS88218/36 BGA Pin Description
Symbol
A
0
, A
1
A
DQ
A
DQ
B
DQ
C
DQ
D
B
A
, B
B
, B
C
, B
D
NC
NC
CK
BW
GW
E
1
E
3
E
2
G
ADV
ADSC, ADSP
ZZ
FT
LBO
PE
Type
I
I
Description
Address field LSBs and Address Counter Preset Inputs
Address Inputs
I/O
Data Input and Output pins
I
Byte Write Enable for DQ
A
, DQ
B
, DQ
C
, DQ
D
I/Os; active low
No Connect
No Connect
Clock Input Signal; active high
Byte Write—Writes all enabled bytes; active low
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active l0w
Address Strobe (Processor, Cache Controller); active low
Sleep mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Parity Enable; active low (119-bump BGA only)
FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low
Drive])
I
I
I
I
I
I
I
I
I
I
I
I
I
ZQ
I
TMS
I
Scan Test Mode Select
TDI
I
Scan Test Data In
TDO
O
Scan Test Data Out
TCK
I
Scan Test Clock
MCL
Must Connect Low
SCD
V
DD
V
SS
V
DDQ
Single Cycle Deselect/Dual Cyle Deselect Mode Control
I
Core power supply
I
I/O and Core Ground
I
Output driver power supply
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