參數(shù)資料
型號(hào)： GS881E36AD-133I
廠商： GSI TECHNOLOGY
元件分類： DRAM
英文描述： 512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
中文描述： 256K X 36 CACHE SRAM, 8.5 ns, PBGA165
封裝： 13 X 15 MM, 1 MM PITCH, FBGA-165
文件頁數(shù)： 9/37頁
文件大?。?/td> 662K
代理商： GS881E36AD-133I
GS881E18/36AT-250/225/200/166/150/133
512K x 18, 256K x 36
9Mb Synchronous Burst SRAMs
250 MHz
–
133 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Rev: 1.03 11/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1/29
2001, GSI Technology
Features
Dual Dycle Deselect (DCD) operation
IEEE 1149.1 JTAG-compatible Boundary Scan
2.5 V or 3.3 V +10%/–10% core power supply
2.5 V or 3.3 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC-standard package
Functional Description
Applications
The GS881E18/36AT is a 9,437,184-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1, E2), address burst
control inputs (ADSP, ADSC, ADV) and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
DCD Pipelined Reads
The GS881E18/36AT is a DCD (Dual Cycle Deselect)
pipelined synchronous SRAM. SCD (Single Cycle Deselect)
versions are also available. DCD SRAMs pipeline disable
commands to the same degree as read commands. DCD RAMs
hold the deselect command for one full cycle and then begin
turning off their outputs just after the second rising edge of
clock.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS881E18/36AT operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (V
DDQ
) pins are used to decouple output noise
from the internal circuits and are 3.3 V and 2.5 V compatible.
Parameter Synopsis
-250 -225 -200 -166 -150 -133 Unit
2.5
4.0
4.4
5.0
6.0
280
330
300
270
230
Pipeline
3-1-1-1
t
KQ
tCycle
Curr (x18)
Curr (x36)
2.7
3.0
3.4
3.8
6.7
185
215
4.0
7.5
165
190
ns
ns
mA
mA
255
230
200
Flow
Through
2-1-1-1
t
KQ
tCycle
5.5
5.5
6.0
6.0
6.5
6.5
7.0
7.0
7.5
7.5
8.5
8.5
ns
ns
Curr (x18)
Curr (x36)
175
200
165
190
160
180
150
170
145
165
135
150
mA
mA
相關(guān)PDF資料
PDF描述
GS881E18AD-166T 512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
GS881E18AD-200 512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
GS881E18AD-200I 512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
GS881E18AD-200IT 512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
GS881E18AD-200T 512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS881E36AD-133IT 制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
GS881E36AD-133T 制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
GS881E36AD-150 制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
GS881E36AD-150I 制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
GS881E36AD-150IT 制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
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