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參數(shù)資料
| 型號： | GS880Z36AT-250I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Coaxial Cable; Coaxial RG/U Type:59; Impedance:75ohm; Conductor Size AWG:20; No. Strands x Strand Size:Solid; Jacket Material:Polyvinylchloride (PVC); Leaded Process Compatible:Yes RoHS Compliant: Yes |
| 中文描述： | 9MB的流水線和流量，通過同步唑的SRAM |
| 文件頁數(shù)： | 1/25頁 |
| 文件大?。?/td> | 753K |
| 代理商： | GS880Z36AT-250I |
Rev: 1.02 9/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
1/25
2001, Giga Semiconductor, Inc.
GS880Z18/36AT-250/225/200/166/150/133
9Mb Pipelined and Flow Through
Synchronous NBT SRAM
250 MHz
–
133 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization; Fully pin-compatible with
both pipelined and flow through NtRAM, NoBL and
ZBT SRAMs
2.5 V or 3.3 V +10%/
–
10% core power supply
2.5 V or 3.3 V I/O supply
User-configurable Pipeline and Flow Through mode
LBO pin for Linear or Interleave Burst mode
Pin compatible with 2M, 4M, and 8M devices
Byte write operation (9-bit Bytes)
3 chip enable signals for easy depth expansion
ZZ Pin for automatic power-down
JEDEC-standard 100-lead TQFP package
-250 -225 -200 -166 -150 -133 Unit
Pipeline
3-1-1-1
tCycle
4.0
4.4
Curr
(x18)
Curr
(x32/x36)
330
300
Curr
(x18)
Curr
(x32/x36)
320
295
Flow
Through
2-1-1-1
Curr
(x18)
Curr
(x32/x36)
200
190
Curr
(x18)
Curr
(x32/x36)
200
190
Functional Description
The GS880Z18/36AT is a 9Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS880Z18/36AT may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, meaning that in addition to the
rising edge triggered registers that capture input signals, the
device incorporates a rising-edge-triggered output register. For
read cycles, pipelined SRAM output data is temporarily stored
by the edge triggered output register during the access cycle
and then released to the output drivers at the next rising edge of
clock.
The GS880Z18/36AT is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
Standard 100-pin TQFP package.
t
KQ
2.5
2.7
3.0
5.0
230
270
230
265
3.4
6.0
200
230
195
225
3.8
6.7
185
215
180
210
4.0
7.5
165
190
165
185
ns
ns
mA
mA
mA
mA
3.3 V
280
255
2.5 V
275
250
t
KQ
tCycle
5.5
5.5
6.0
6.0
6.5
6.5
7.0
7.0
7.5
7.5
8.5
8.5
ns
ns
3.3 V
175
165
160
180
160
180
150
170
150
170
145
165
145
165
135
150
135
150
mA
mA
mA
mA
2.5 V
175
165
A
B
C
D
E
F
R
W
R
W
R
W
Q
A
D
B
Q
C
D
D
Q
E
Q
A
D
B
Q
C
D
D
Q
E
Clock
Address
Read/Write
Flow Through
Data I/O
Pipelined
Data I/O
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS880Z18AT-225 | 1 MEGABIT 3.3 VOLT SERIAL CONFIGURATION - NOT RECOMMENDED for NEW DESIGN |
| GS880Z18AT-225I | 9Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS880Z18AT-250 | 9Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS880Z18AT-250I | 2 MG 3.3V OTP PROM (UMC) - NOT RECOMMENDED for NEW DESIGN |
| GS880Z18AT-133 | 9Mb Pipelined and Flow Through Synchronous NBT SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS880Z36BGT-150 | 制造商:GSI Technology 功能描述:9MB SYNCH BURST SRAM 256K X 36 880 |
| GS880Z36BGT-150I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:9Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS880Z36BGT-150IV | 制造商:GSI 制造商全稱:GSI Technology 功能描述:9Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS880Z36BGT-150V | 制造商:GSI 制造商全稱:GSI Technology 功能描述:9Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS880Z36BGT-200 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:9Mb Pipelined and Flow Through Synchronous NBT SRAM |
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