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參數(shù)資料
| 型號(hào)： | GS880Z18T-80I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Header; No. of Contacts:24; Pitch Spacing:0.079"; No. of Rows:2; Gender:Male; Series:1552; Body Material:Glass Filled Polyester; Connector Retention Style:Latch/Ejector; Contact Termination:Through Hole; Housing Style:Right-Angle RoHS Compliant: Yes |
| 中文描述： | 8MB的流水線和流量，通過(guò)同步唑靜態(tài)存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 6/25頁(yè) |
| 文件大小： | 424K |
| 代理商： | GS880Z18T-80I |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)當(dāng)前第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)
Rev: 1.04 3/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
6/25
2000, Giga Semconductor, Inc.
O
Preliminary
GS880F18/36T-10/11/11.5/12/14
GS880F18/32/36 Block Diagram
A1
A0
A0
A1
D0
D1
Q1
Q0
Counter
Load
D
Q
D
Q
Register
Register
D
Q
Register
D
Q
Register
D
Q
Register
D
Q
Register
D
Q
Register
D
Q
Register
D
Q
R
D
Q
R
A0-An
LBO
ADV
CK
ADSC
ADSP
GW
BW
B
A
B
B
B
C
B
D
E
1
E
2
E
3
G
ZZ
Power Down
Control
Memory
Array
4
A
Q
D
1
0
36
36
DQx0-DQx9
Note: Only x36 version shown for simplicity.
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| GS88118T-11I | x18 Fast Synchronous SRAM |
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|---|---|
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| GS880Z32BGT-150IV | 制造商:GSI 制造商全稱(chēng):GSI Technology 功能描述:9Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS880Z32BGT-150V | 制造商:GSI 制造商全稱(chēng):GSI Technology 功能描述:9Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS880Z32BGT-200IV | 制造商:GSI 制造商全稱(chēng):GSI Technology 功能描述:9Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS880Z32BGT-200V | 制造商:GSI 制造商全稱(chēng):GSI Technology 功能描述:9Mb Pipelined and Flow Through Synchronous NBT SRAM |
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