參數(shù)資料
型號(hào)： GS880Z18AT-133
廠商： Electronic Theatre Controls, Inc.
英文描述： 9Mb Pipelined and Flow Through Synchronous NBT SRAM
中文描述： 9MB的流水線和流量，通過(guò)同步唑的SRAM
文件頁(yè)數(shù)： 11/25頁(yè)
文件大?。?/td> 753K
代理商： GS880Z18AT-133
Rev: 1.02 9/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
11/25
2001, Giga Semiconductor, Inc.
GS880Z18/36AT-250/225/200/166/150/133
Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
Mode Pin Functions
Note:
There is a pull-up device on the and FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will
operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
BPR 1999.05.18
Mode Name
Pin Name
State
L
H
L or NC
Function
Linear Burst
Interleaved Burst
Active
Standby, I
DD
= I
SB
Burst Order Control
LBO
Power Down Control
ZZ
H
Note: The burst counter wraps to initial state on the 5th clock.
I
nterleaved Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
相關(guān)PDF資料
PDF描述
GS880Z18AT-133I 9Mb Pipelined and Flow Through Synchronous NBT SRAM
GS880Z18AT-150 9Mb Pipelined and Flow Through Synchronous NBT SRAM
GS880Z18AT-150I 9Mb Pipelined and Flow Through Synchronous NBT SRAM
GS880Z18AT-166 9Mb Pipelined and Flow Through Synchronous NBT SRAM
GS880Z18AT-166I 9Mb Pipelined and Flow Through Synchronous NBT SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS880Z18AT-133I 制造商:GSI 制造商全稱(chēng):GSI Technology 功能描述:9Mb Pipelined and Flow Through Synchronous NBT SRAM
GS880Z18AT-150 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:9Mb Pipelined and Flow Through Synchronous NBT SRAM
GS880Z18AT-150I 制造商:GSI 制造商全稱(chēng):GSI Technology 功能描述:9Mb Pipelined and Flow Through Synchronous NBT SRAM
GS880Z18AT-166 制造商:GSI 功能描述: 制造商:GSI Technology 功能描述:
GS880Z18AT-166I 制造商:GSI 制造商全稱(chēng):GSI Technology 功能描述:9Mb Pipelined and Flow Through Synchronous NBT SRAM
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