參數(shù)資料
型號(hào)： GS8662T06BD-350T
廠商： GSI TECHNOLOGY
元件分類(lèi)： SRAM
英文描述： 8M X 8 DDR SRAM, 0.45 ns, PBGA165
封裝： 13 X 15 MM, 1 MM PITCH, FPBGA-165
文件頁(yè)數(shù)： 31/33頁(yè)
文件大?。?/td> 651K
代理商： GS8662T06BD-350T
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 3/2011
7/33
2011, GSI Technology
GS8662T20/38BD-550/500/450/400/350
GS8662T06/11BD-500/450/400/350
Background
Common I/O SRAMs, from a system architecture point of view, are attractive in read dominated or block transfer applications.
Therefore, the SigmaDDR-II+ SRAM interface and truth table are optimized for burst reads and writes. Common I/O SRAMs are
unpopular in applications where alternating reads and writes are needed because bus turnaround delays can cut high speed
Common I/O SRAM data bandwidth in half.
Burst Operations
Read and write operations are "Burst" operations. In every case where a read or write command is accepted by the SRAM, it will
respond by issuing or accepting two beats of data, executing a data transfer on subsequent rising edges of K and K, as illustrated in
the timing diagrams. It is not possible to stop a burst once it starts. Two beats of data are always transferred. This means that it is
possible to load new addresses every K clock cycle. Addresses can be loaded less often, if intervening deselect cycles are inserted.
Deselect Cycles
Chip Deselect commands are pipelined to the same degree as read commands. This means that if a deselect command is applied to
the SRAM on the next cycle after a read command captured by the SRAM, the device will complete the two beat read data transfer
and then execute the deselect command, returning the output drivers to High-Z. A high on the LD pin prevents the RAM from
loading read or write command inputs and puts the RAM into deselect mode as soon as it completes all outstanding burst transfer
operations.
SigmaDDR-II+ B2 SRAM Read Cycles
The SRAM executes pipelined reads. The status of the Address, LD and R/W pins are evaluated on the rising edge of K. The read
command (LD low and R/W high) is clocked into the SRAM by a rising edge of K.
SigmaDDR-II+ B2 SRAM Write Cycles
The status of the Address, LD and R/W pins are evaluated on the rising edge of K. The SRAM executes "late write" data transfers.
Data in is due at the device inputs on the rising edge of K following the rising edge of K clock used to clock in the write command
(LD and R/W low) and the write address. To complete the remaining beat of the burst of two write transfer, the SRAM captures
data in on the next rising edge of K, for a total of two transfers per address load.
相關(guān)PDF資料
PDF描述
GS8672Q38BE-500I 2M X 36 QDR SRAM, 0.45 ns, PBGA165
GS880F32AGT-5.5IT 256K X 32 CACHE SRAM, 5.5 ns, PQFP100
GS880F32BGT-7IT 256K X 32 CACHE SRAM, 7 ns, PQFP100
GSAA07C-Q01 SNAP ACTING/LIMIT SWITCH, SPDT, MOMENTARY, 0.1A, 50VDC, PANEL MOUNT
GSAC36C-6Q02 SNAP ACTING/LIMIT SWITCH, SPDT, MOMENTARY, 0.1A, 50VDC, PANEL MOUNT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8662T06BD-450 制造商:GSI Technology 功能描述:GS8662T06BD-450 - Trays
GS8662T06BD-500 制造商:GSI Technology 功能描述:GS8662T06BD-500 - Trays
GS8662T06BD-550 制造商:GSI Technology 功能描述:GS8662T06BD-550 - Trays
GS8662T07BD-450 制造商:GSI Technology 功能描述:165 FBGA - Bulk
GS8662T08BD-400 制造商:GSI Technology 功能描述:165 FBGA - Bulk
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