參數(shù)資料
型號: GS8662S08GE-250I
廠商: GSI TECHNOLOGY
元件分類: DRAM
英文描述: 72Mb Burst of 2 DDR SigmaSIO-II SRAM
中文描述: 8M X 8 DDR SRAM, 0.45 ns, PBGA165
封裝: 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, MO-216CAB-1, FPBGA-165
文件頁數(shù): 6/37頁
文件大?。?/td> 960K
代理商: GS8662S08GE-250I
Pin Description Table
Symbol
Description
Type
Comments
SA
Synchronous Address Inputs
Input
NC
No Connect
R/W
Read/Write Contol Pin
Input
Write Active Low; Read Active High
NW0–NW1
Synchronous Nybble Writes
Input
Active Low
x08 Version
BW0–BW1
Synchronous Byte Writes
Input
Active Low
x18 Version
BW0–BW3
Synchronous Byte Writes
Input
Active Low
x36 Version
K
Input Clock
Input
Active High
C
Output Clock
Input
Active High
TMS
Test Mode Select
Input
TDI
Test Data Input
Input
TCK
Test Clock Input
Input
TDO
Test Data Output
Output
V
REF
HSTL Input Reference Voltage
Input
ZQ
Output Impedance Matching Input
Input
K
Input Clock
Input
Active Low
C
Output Clock
Output
Active Low
D
OFF
DLL Disable
Active Low
LD
Synchronous Load Pin
Active Low
CQ
Output Echo Clock
Output
Active Low
CQ
Output Echo Clock
Output
Active High
Dn
Synchronous Data Inputs
Input
Qn
Synchronous Data Outputs
Output
V
DD
Power Supply
Supply
1.8 V Nominal
V
DDQ
Isolated Output Buffer Supply
Supply
1.8 or 1.5 V Nominal
V
SS
Power Supply: Ground
Supply
Notes:
1.
2.
C, C, K, or K cannot be set to V
REF
voltage.
When ZQ pin is directly connected to V
DD
, output impedance is set to minimum value and it cannot be connected to ground or left
unconnected.
NC = Not Connected to die or any other pin
3.
Preliminary
GS8662S08/09/18/36E-333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 9/2005
6/37
2005, GSI Technology
相關PDF資料
PDF描述
GS8662S08GE-300 72Mb Burst of 2 DDR SigmaSIO-II SRAM
GS8662S08GE-300I 72Mb Burst of 2 DDR SigmaSIO-II SRAM
GS8662S08GE-333 72Mb Burst of 2 DDR SigmaSIO-II SRAM
GS8662S08GE-333I 72Mb Burst of 2 DDR SigmaSIO-II SRAM
GS8662S09E-167 72Mb Burst of 2 DDR SigmaSIO-II SRAM
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