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參數(shù)資料
| 型號： | GS8644Z72C-250I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Header; No. of Contacts:20; Pitch Spacing:0.079"; No. of Rows:2; Gender:Male; Series:1552; Body Material:Glass Filled Polyester; Connector Retention Style:Latch/Ejector; Contact Termination:Through Hole; Housing Style:Right-Angle RoHS Compliant: Yes |
| 中文描述： | 72Mb流水線和流量，通過同步唑的SRAM |
| 文件頁數(shù)： | 3/39頁 |
| 文件大?。?/td> | 1174K |
| 代理商： | GS8644Z72C-250I |
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GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
3/39
2003, GSI Technology
GS8644Z72 209-Bump BGA Pin Description
Symbol
Type
Description
A
0
, A
1
I
Address field LSBs and Address Counter Preset Inputs.
A
I
Address Inputs
DQ
A
DQ
B
DQ
C
DQ
D
DQ
E
DQ
F
DQ
G
DQ
H
I/O
Data Input and Output pins
B
A
, B
B
I
Byte Write Enable for DQ
A
, DQ
B
I/Os; active low
B
C
,B
D
I
Byte Write Enable for DQ
C
, DQ
D
I/Os; active low
B
E
, B
F
, B
G
,B
H
I
Byte Write Enable for DQ
E
, DQ
F
, DQ
G
, DQ
H
I/Os; active low
NC
—
No Connect
CK
I
Clock Input Signal; active high
E
1
I
Chip Enable; active low
E
3
I
Chip Enable; active low
E
2
I
Chip Enable; active high
G
I
Output Enable; active low
ADV
I
Burst address counter advance enable
ZZ
I
Sleep Mode control; active high
FT
I
Flow Through or Pipeline mode; active low
LBO
I
Linear Burst Order mode; active low
MCH
I
Must Connect High
MCH
I
Must Connect High
MCL
Must Connect Low
W
I
Write Enable; active low
ZQ
I
FLXDrive Output Impedance Control
Low = Low Impedance [High Drive],
High = High Impedance [Low Drive]
CKE
I
Clock Enable; active low
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