參數(shù)資料
型號(hào)： GS8644Z36E-250
廠商： Electronic Theatre Controls, Inc.
英文描述： 72Mb Pipelined and Flow Through Synchronous NBT SRAM
中文描述： 72Mb流水線和流量，通過同步唑的SRAM
文件頁數(shù)： 29/39頁
文件大小： 1174K
代理商： GS8644Z36E-250
Product Preview
GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
29/39
2003, GSI Technology
JTAG Tap Controller State Diagram
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-
tate testing of other devices in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
Select DR
Capture DR
0
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
1
Select IR
Capture IR
0
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
1
Test Logic Reset
Run Test Idle
0
1
0
1
1
0
1
1
1
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
1
1
1
1
相關(guān)PDF資料
PDF描述
GS8644Z36E-250I 72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8644Z18E-133 CONN 2MM SKT 20POS THRU-BRD SMD
GS8644Z36E-133 Header; No. of Contacts:10; Pitch Spacing:0.079"; No. of Rows:2; Gender:Male; Series:1552; Body Material:Glass Filled Polyester; Connector Retention Style:Latch/Ejector; Housing Style:Straight; Leaded Process Compatible:Yes RoHS Compliant: Yes
GS8644Z36E-133I Header; No. of Contacts:10; Pitch Spacing:0.079"; No. of Rows:2; Gender:Male; Series:1552; Body Material:Glass Filled Polyester; Connector Retention Style:Latch/Ejector; Contact Termination:Through Hole; Housing Style:Right-Angle RoHS Compliant: Yes
GS8644Z36E-150 Header; No. of Contacts:10; Pitch Spacing:0.079"; No. of Rows:2; Gender:Male; Series:1552; Body Material:Glass Filled Polyester; Connector Retention Style:Latch/Ejector; Contact Termination:Through Hole; Housing Style:Right-Angle RoHS Compliant: Yes
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8644Z36E-250I 制造商:GSI Technology 功能描述:SRAM SYNC SGL 2.5V/3.3V 72MBIT 2MX36 6.5NS/2.5NS 165FBGA - Trays
GS8644Z36E-250IV 制造商:GSI Technology 功能描述:SRAM SYNC SGL 1.8V/2.5V 72MBIT 2MX36 6.5NS/2.3NS 165FPBGA - Trays
GS8644Z36E-250V 制造商:GSI Technology 功能描述:SRAM SYNC SGL 1.8V/2.5V 72MBIT 2MX36 6.5NS/2.3NS 165FBGA - Trays
GS8644Z36GB-150 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 72MBIT 2MX36 7.5NS/3.8NS 119FPBGA - Trays
GS8644Z36GE-166IV 制造商:GSI Technology 功能描述:SRAM SYNC SGL 1.8V/2.5V 72MBIT 2MX36 7NS/2.9NS 165FBGA - Trays
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