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參數(shù)資料
| 型號： | GS8644Z18B-133I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| 中文描述： | 72Mb流水線和流量，通過同步唑的SRAM |
| 文件頁數(shù)： | 29/39頁 |
| 文件大?。?/td> | 1174K |
| 代理商： | GS8644Z18B-133I |
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GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
29/39
2003, GSI Technology
JTAG Tap Controller State Diagram
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-
tate testing of other devices in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
Select DR
Capture DR
0
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
1
Select IR
Capture IR
0
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
1
Test Logic Reset
Run Test Idle
0
1
0
1
1
0
1
1
1
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
1
1
1
1
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PDF描述 |
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| GS8644Z18B-150 | 72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8644Z18B-150I | 72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8644Z18B-166 | 72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8644Z18B-166I | 72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8644Z18B-200 | 72Mb Pipelined and Flow Through Synchronous NBT SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS8644Z18B-133IV | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 72MBIT 4MX18 8.5NS/4NS 119FPBGA - Trays |
| GS8644Z18B-133V | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 72MBIT 4MX18 8.5NS/4NS 119FPBGA - Trays |
| GS8644Z18B-150 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 72MBIT 4MX18 7.5NS/3.8NS 119FPBGA - Trays |
| GS8644Z18B-150I | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 72MBIT 4MX18 7.5NS/3.8NS 119FPBGA - Trays |
| GS8644Z18B-150IV | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 72MBIT 4MX18 7.5NS/3.8NS 119FPBGA - Trays |
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