參數(shù)資料
型號(hào)： GS8642Z36B-200
廠(chǎng)商： GSI TECHNOLOGY
元件分類(lèi)： DRAM
英文描述： 72Mb Pipelined and Flow Through Synchronous NBT SRAM
中文描述： 2M X 36 ZBT SRAM, 7.5 ns, PBGA119
封裝： 14 X 22 MM, 1.27 MM PITCH, FPBGA-119
文件頁(yè)數(shù)： 9/34頁(yè)
文件大?。?/td> 872K
代理商： GS8642Z36B-200
Synchronous Truth Table
Operation
Type
Address
CK CKE ADV W Bx E
1
E
2
E
3
G ZZ
DQ
Notes
Read Cycle, Begin Burst
R
External
L-H
L
L
H
X
L
H
L
L
L
Q
Read Cycle, Continue Burst
B
Next
L-H
L
H
X
X
X
X
X
L
L
Q
1,10
NOP/Read, Begin Burst
R
External
L-H
L
L
H
X
L
H
L
H
L
High-Z
2
Dummy Read, Continue Burst
B
Next
L-H
L
H
X
X
X
X
X
H
L
High-Z
1,2,10
Write Cycle, Begin Burst
W
External
L-H
L
L
L
L
L
H
L
X
L
D
3
Write Cycle, Continue Burst
B
Next
L-H
L
H
X
L
X
X
X
X
L
D
1,3,10
Write Abort, Continue Burst
B
Next
L-H
L
H
X
H
X
X
X
X
L
High-Z 1,2,3,10
Deselect Cycle, Power Down
D
None
L-H
L
L
X
X
H
X
X
X
L
High-Z
Deselect Cycle, Power Down
D
None
L-H
L
L
X
X
X
X
H
X
L
High-Z
Deselect Cycle, Power Down
D
None
L-H
L
L
X
X
X
L
X
X
L
High-Z
Deselect Cycle
D
None
L-H
L
L
L
H
L
H
L
X
L
High-Z
1
Deselect Cycle, Continue
D
None
L-H
L
H
X
X
X
X
X
X
L
High-Z
1
Sleep Mode
None
X
X
X
X
X
X
X
X
X
H
High-Z
Clock Edge Ignore, Stall
Current
L-H
H
X
X
X
X
X
X
X
L
-
4
Notes:
1.
Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese-
lect cycle is executed first.
Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W
pin is sampled low but no Byte Write pins are active so no write operation is performed.
G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during
write cycles.
If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write
signals are Low
All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
Wait states can be inserted by setting CKE high.
This device contains circuitry that ensures all outputs are in High Z during power-up.
A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
2.
3.
4.
5.
6.
7.
8.
9.
Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
9/34
2004, GSI Technology
相關(guān)PDF資料
PDF描述
GS8642Z36B-200I 72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8642Z36B-250 72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8642Z36B-250I 72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8642Z36B-300 72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8642Z36B-300I 72Mb Pipelined and Flow Through Synchronous NBT SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8642Z36B-200I 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 72MBIT 2MX36 7.5NS/3NS 119FBGA - Trays
GS8642Z36B-250 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 72MBIT 2MX36 6.5NS/2.5NS 119FBGA - Trays
GS8642Z36B-250I 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 72MBIT 2MX36 6.5NS/2.5NS 119FBGA - Trays
GS8642Z36B-250M 制造商:GSI Technology 功能描述:72MB PIPELINED AND FLOW THROUGH SYNCHRONOUS NBT SRAM - Bulk
GS8642Z36B-300 制造商:GSI 制造商全稱(chēng):GSI Technology 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠(chǎng)商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*