參數(shù)資料
型號(hào)： GS841Z36AGT-180
廠商： GSI TECHNOLOGY
元件分類： DRAM
英文描述： 4Mb Pipelined and Flow Through Synchronous NBT SRAMs
中文描述： 128K X 36 ZBT SRAM, 8 ns, PQFP100
封裝： ROHS COMPLIANT, TQFP-100
文件頁(yè)數(shù)： 22/30頁(yè)
文件大小： 495K
代理商： GS841Z36AGT-180
GS841Z18/36AT-180/166/150/100
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 11/2004
22/30
2001, GSI Technology
JTAG Tap Controller State Diagram
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-
tate testing of other devices in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is
still determined by its input pins.
Select DR
Capture DR
0
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
1
Select IR
Capture IR
0
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
1
Test Logic Reset
Run Test Idle
0
1
0
1
1
0
1
1
1
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
1
1
1
1
相關(guān)PDF資料
PDF描述
GS841Z36AGT-180I 4Mb Pipelined and Flow Through Synchronous NBT SRAMs
GS841Z36AT-100 4Mb Pipelined and Flow Through Synchronous NBT SRAMs
GS841Z36AT-100I 4Mb Pipelined and Flow Through Synchronous NBT SRAMs
GS8644V72C-250 4M x 18, 2M x 36, 1M x 72 72Mb S/DCD Sync Burst SRAMs
GS8644V72C-250I 4M x 18, 2M x 36, 1M x 72 72Mb S/DCD Sync Burst SRAMs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS841Z36AGT-180I 制造商:GSI 制造商全稱:GSI Technology 功能描述:4Mb Pipelined and Flow Through Synchronous NBT SRAMs
GS841Z36AT-100 制造商:GSI 制造商全稱:GSI Technology 功能描述:4Mb Pipelined and Flow Through Synchronous NBT SRAMs
GS841Z36AT-100I 制造商:GSI 制造商全稱:GSI Technology 功能描述:4Mb Pipelined and Flow Through Synchronous NBT SRAMs
GS841Z36AT-150 制造商:GSI 制造商全稱:GSI Technology 功能描述:4Mb Pipelined and Flow Through Synchronous NBT SRAMs
GS841Z36AT-150I 制造商:GSI 制造商全稱:GSI Technology 功能描述:4Mb Pipelined and Flow Through Synchronous NBT SRAMs
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*