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參數(shù)資料
| 型號： | GS8330DW72C-200 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DC/DC變換器 |
| 英文描述： | 1 watt dc-dc converters |
| 中文描述： | 1瓦的DC - DC轉(zhuǎn)換器 |
| 文件頁數(shù)： | 5/30頁 |
| 文件大小： | 583K |
| 代理商： | GS8330DW72C-200 |
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Rev: 1.00 6/2003
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
5/30
2003, GSI Technology, Inc.
Preliminary
GS8330DW36/72C-250/200
Read Operations
Pipelined Read
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2,
and E3) are active, the write enable input signal (W) is deasserted high, and ADV is asserted low. The address presented to the
address inputs is latched into the address register and presented to the memory core and control logic. The control logic determines
that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge
of clock the read data is allowed to propagate through the output register and onto the output pins.
Write Operations
Write operation occurs when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2, and
E3) are active, the write enable input signal (W) is asserted low, and ADV is asserted low.
Single Data Rate Pipelined Read
F
D
Address
Read
CK
E
QC
QD
CQ
Read
Deselect
Read
Read
A
XX
C
Key
Hi-Z
Access
ADV
QA
/E
1
/W
DQ
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