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參數(shù)資料
| 型號： | GS8330DW36C-250I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | RECTIFIER FAST-RECOVERY SINGLE 1A 50V 30A-ifsm 1.2V-vf 200ns 5uA-ir DO-41 1K/BULK |
| 中文描述： | 雙晚寫SigmaRAM |
| 文件頁數(shù)： | 10/30頁 |
| 文件大小： | 583K |
| 代理商： | GS8330DW36C-250I |
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Rev: 1.00 6/2003
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
10/30
2003, GSI Technology, Inc.
Preliminary
GS8330DW36/72C-250/200
Programmable Enables
Σ
RAMs feature two user-programmable chip enable inputs, E2 and E3. The sense of the inputs, whether they function as active
low or active high inputs, is determined by the state of the programming inputs, EP2 and EP3. For example, if EP2 is held at V
DD
,
E2 functions as an active high enable. If EP2 is held to V
SS
, E2 functions as an active low chip enable input.
Programmability of E2 and E3 allows four banks of depth expansion to be accomplished with no additional logic. By programming
the enable inputs of four SRAMs in binary sequence (00, 01, 10, 11) and driving the enable inputs with two address inputs, four
SRAMs can be made to look like one larger RAM to the system.
Example Four Bank Depth Expansion Schematic—
Σ
1x1Dp
A
CK
E1
E2
E3
W
DQ
CQ
A
0
–A
n
CK
W
DQ
0
–DQ
n
Bank 0
Bank 1
Bank 2
Bank 3
Bank Enable Truth Table
EP2
V
SS
V
SS
V
DD
V
DD
EP3
V
SS
V
DD
V
SS
V
DD
E2
E3
Bank 0
Bank 1
Bank 2
Bank 3
Active Low
Active Low
Active High
Active High
Active Low
Active High
Active Low
Active High
E1
A
n – 1
A
n
A
0
–A
n – 2
A
n – 1
A
n
A
0
–A
n – 2
A
n – 1
A
n
A
0
–A
n – 2
A
n – 1
A
n
A
0
–A
n – 2
A
CK
E2
E3
W
DQ
CQ
A
CK
E2
E3
W
DQ
CQ
A
CK
E2
E1
E3
W
DQ
CQ
E1
E1
CQ
EP2
EP3
0
0
EP2
EP3
1
0
EP2
EP3
0
1
EP2
EP3
1
1
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