參數(shù)資料
型號(hào)： GS8330DW36C-200
廠商： Electronic Theatre Controls, Inc.
英文描述： DIODE ZENER SINGLE 1000mW 75Vz 3.3mA-Izt 0.05 5uA-Ir 56Vr DO41-GLASS 5K/REEL
中文描述： 雙晚寫(xiě)SigmaRAM
文件頁(yè)數(shù)： 9/30頁(yè)
文件大小： 583K
代理商： GS8330DW36C-200
Rev: 1.00 6/2003
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
9/30
2003, GSI Technology, Inc.
Preliminary
GS8330DW36/72C-250/200
SigmaRAM Double Late Write SRAM Burst Writes with Counter Wrap-around
Burst Order
The burst address counter wraps around to its initial state after four internal addresses (the loaded address and three more) have
been accessed. SigmaRAMs always count in linear burst order.
Linear Burst Order
Note: The burst counter wraps to initial state on the 5th rising edge of clock.
Echo Clock
SRAMs feature Echo Clocks, CQ1, CQ2, CQ1, and CQ2 that track the performance of the output drivers. The Echo Clocks are
delayed copies of the main RAM clock, CK. Echo Clocks are designed to track changes in output driver delays due to variance in
die temperature and supply voltage. The Echo Clocks are designed to fire with the rest of the data output drivers. SigmaRAMs
provide both in-phase, or true, Echo Clock outputs (CQ1 and CQ2) and inverted Echo Clock outputs (CQ1 and CQ2).
It should be noted that deselection of the RAM via E2 and E3 also deselects the Echo Clock output drivers. The deselection of
Echo Clock drivers is always pipelined to the same degree as output data.
Deselection of the RAM via E1 does not deactivate the
Echo Clocks.
A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
ADV
Counter Wraps
D1
D2
D0
/E
1
/W
CQ
DQ
D2
D3
Write
Continue
XX
Internal
Address
A2
A3
A0
A1
A2
CK
Address
A2
XX
Continue
Continue
Continue
XX
XX
XX
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