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參數(shù)資料
| 型號： | GS8330DW36-250 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DC/DC變換器 |
| 英文描述： | 1 watt dc-dc converters |
| 中文描述： | 1瓦的DC - DC轉(zhuǎn)換器 |
| 文件頁數(shù)： | 25/30頁 |
| 文件大?。?/td> | 583K |
| 代理商： | GS8330DW36-250 |
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Rev: 1.00 6/2003
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
25/30
2003, GSI Technology, Inc.
Preliminary
GS8330DW36/72C-250/200
the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the Boundary Scan Register
between the TDI and TDO pins. The Update-DR controller state transfers the contents of boundary scan cells into the holding register of
each cell associated with an output pin on the RAM.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The
EXTEST command does not block or override the RAM’s input pins (except CK); therefore, the RAM’s internal state is still determined by its
input pins.
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST
command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK
when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected,
the state of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are sampled
and transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state. Boundary Scan Register con-
tents may then be shifted serially through the register using the Shift-DR command or the controller can be skipped to the Update-DR com-
mand. When the controller is placed in the Update-DR state, a RAM that has a fully compliant EXTEST function drives out the value of the
Boundary Scan Register location associated with which each output pin.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID
register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any
time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z/PRELOAD
The SAMPLE-Z instruction operates exactly like SAMPLE/PRELOAD except that loading the SAMPLE-Z instruction forces all the RAM’s
output drivers, except TDO, to an inactive drive state (high-Z).
RFU
These instructions are reserved for future use.
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| GS84018 | Connectors |
| GS84018AB-100 | Time-Delay Relay Relay Type:Time-Delay |
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