參數(shù)資料
型號(hào)： GS832418B-225I
廠商： GSI TECHNOLOGY
元件分類： DRAM
英文描述： 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
中文描述： 2M X 18 CACHE SRAM, 6 ns, PBGA119
封裝： 14 X 22 MM, 1.27 MM PITCH, BGA-119
文件頁(yè)數(shù)： 40/46頁(yè)
文件大?。?/td> 1149K
代理商： GS832418B-225I
Rev: 1.00 10/2001
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
40/46
2001, Giga Semiconductor, Inc.
Preliminary
GS832418(B/C)/GS832436(B/C)/GS832472(C)
Notes
:
1.
Depending on the package, some input pads of the scan chain may not be connected to any external pin. In such case: LBO = 1, ZQ = 1,
PE = 0, SD = 0, ZZ = 0, FT = 1, DP = 1, and SCD = 1.
Every DQ pad consists of two scan registers—D is for input capture, and Q is for output capture.
A single register (#194) for controlling tristate of all the DQ pins is at the end of the scan chain (i.e., the last bit shifted in this tristate control
is effective after JTAG EXTEST instruction is executed.
1 = no connect, internally set to logic value 1
0 = no connect, internally set to logic value 0
X = no connect, value is undefined
2.
3.
4.
5.
6.
GS832418/36/72 Boundary Scan Chain Order
Order
x72
x36
x18
Bump
x72
x36
x18
1(TBD)
相關(guān)PDF資料
PDF描述
GS832418B-250 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
GS832418B-250I 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
GS832418C-133 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
GS832418C-133I 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
GS832418C-150 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8324Z36B-133 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 36MBIT 1MX36 10NS/4NS 119FBGA - Trays
GS8324Z36B-200I 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 36MBIT 1MX36 7.5NS/3NS 119FBGA - Trays
GS8324Z72C200 制造商:G.S.I. 功能描述:
GS8342D06BD-350 制造商:GSI Technology 功能描述:165 FBGA - Bulk
GS8342D06BD-500 制造商:GSI Technology 功能描述:165 FBGA - Bulk
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