參數(shù)資料
型號(hào): GS832418B-225
廠商: GSI TECHNOLOGY
元件分類: DRAM
英文描述: 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
中文描述: 2M X 18 CACHE SRAM, 6 ns, PBGA119
封裝: 14 X 22 MM, 1.27 MM PITCH, BGA-119
文件頁(yè)數(shù): 37/46頁(yè)
文件大?。?/td> 1149K
代理商: GS832418B-225
Rev: 1.00 10/2001
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
37/46
2001, Giga Semiconductor, Inc.
Preliminary
GS832418(B/C)/GS832436(B/C)/GS832472(C)
JTAG TAP Instruction Set Summary
Instruction
EXTEST
IDCODE
Code
000
001
Description
Notes
1
1, 2
Places the Boundary Scan Register between TDI and TDO.
Preloads ID Register and places it between TDI and TDO.
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Forces all RAM output drivers to High-Z.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
GSI private instruction.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
Places Bypass Register between TDI and TDO.
SAMPLE-Z
010
1
RFU
011
1
SAMPLE/
PRELOAD
GSI
100
1
101
1
RFU
110
1
BYPASS
111
1
Notes:
1.
2.
Instruction codes expressed in binary, MSB on left, LSB on right.
Default instruction automatically loaded at power-up and in test-logic-reset state.
相關(guān)PDF資料
PDF描述
GS832418B-225I 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
GS832418B-250 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
GS832418B-250I 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
GS832418C-133 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
GS832418C-133I 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
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