
GS8322ZV18(B/E)/GS8322ZV36(B/E)/GS8322ZV72(C)
36Mb Pipelined and Flow Through 
Synchronous NBT SRAM
250 MHz
–
133 MHz
 1.8 V V
DD
1.8 V I/O
119, 165 & 209 BGA
Commercial Temp
Industrial Temp
Rev:  1.03a  2/2006
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1/39
 2002, GSI Technology
Features
 NBT (No Bus Turn Around) functionality allows zero wait 
Read-Write-Read bus utilization; fully pin-compatible with 
both pipelined and flow through NtRAM, NoBL and 
ZBT SRAMs
 1.8 V +10%/–10% core power supply
 1.8 V I/O supply
 User-configurable Pipeline and Flow Through mode
 ZQ mode pin for user-selectable high/low output drive
 IEEE 1149.1 JTAG-compatible Boundary Scan
 LBO pin for Linear or Interleave Burst mode
 Pin-compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices
 Byte write operation (9-bit Bytes)
 3 chip enable signals for easy depth expansion
 ZZ Pin for automatic power-down
 JEDEC-standard 119-, 165- or 209-Bump BGA package
 Pb-Free packages available
Functional Description
The GS8322ZV18/36/72 is a 36Mbit Synchronous Static 
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or 
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus 
bandwidth by eliminating the need to insert deselect cycles 
when the device is switched from read to write cycles. 
Because it is a synchronous device, address, data inputs, and 
read/write control inputs are captured on the rising edge of the 
input clock. Burst order control (LBO) must be tied to a power 
rail for proper operation. Asynchronous inputs include the 
Sleep mode enable (ZZ) and Output Enable. Output Enable can 
be used to override the synchronous control of the output 
drivers and turn the RAM's output drivers off at any time. 
Write cycles are internally self-timed and initiated by the rising 
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs 
and simplifies input signal timing. 
The GS8322ZV18/36/72  may be configured by the user to 
operate in Pipeline or Flow Through mode. Operating as a 
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device 
incorporates a rising edge triggered output register. For read 
cycles, pipelined SRAM output data is temporarily stored by 
the edge-triggered output register during the access cycle and 
then released to the output drivers at the next rising edge of 
clock. 
The GS8322ZV18/36/72 is implemented with GSI's high 
performance CMOS technology and is available in a JEDEC-
standard 119-bump, 165-bump or 209-bump BGA package. 
Parameter Synopsis
-250 -225 -200 -166 -150 -133 Unit
2.5
3.0
4.0
4.4
5.0
6.0
Pipeline
3-1-1-1
t
KQ(x18/x36)
t
KQ(x72)
tCycle
Curr 
(x18)
Curr 
(x36)
Curr 
(x72)
t
KQ
tCycle
Curr 
(x18)
Curr 
(x36)
Curr 
(x72)
2.7
3.0
3.0
3.0
3.5
3.5
3.8
3.8
6.7
4.0
4.0
7.5
ns
ns
ns
285
350
440
6.5
6.5
205
235
315
265
320
410
7.0
7.0
195
225
295
245
295
370
7.5
7.5
185
210
265
220
260
320
8.0
8.0
175
200
255
210
240
300
8.5
8.5
165
190
240
185
215
265
8.5
8.5
155
175
230
mA
mA
mA
ns
ns
mA
mA
mA
Flow 
Through
2-1-1-1