參數(shù)資料
型號(hào): GS8322Z18B-133V
廠商: GSI TECHNOLOGY
元件分類(lèi): DRAM
英文描述: 36Mb Pipelined and Flow Through Synchronous NBT SRAM
中文描述: 2M X 18 ZBT SRAM, 8.5 ns, PBGA119
封裝: 14 X 22 MM, 1.27 MM PITCH, FPBGA-119
文件頁(yè)數(shù): 29/39頁(yè)
文件大小: 973K
代理商: GS8322Z18B-133V
JTAG TAP Instruction Set Summary
Instruction
Code
Description
Notes
EXTEST
000
Places the Boundary Scan Register between TDI and TDO.
1
IDCODE
001
Preloads ID Register and places it between TDI and TDO.
1, 2
SAMPLE-Z
010
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Forces all RAM output drivers to High-Z.
1
RFU
011
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
SAMPLE/
PRELOAD
100
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
1
GSI
101
GSI private instruction.
1
RFU
110
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
BYPASS
111
Places Bypass Register between TDI and TDO.
1
Notes:
1.
2.
Instruction codes expressed in binary, MSB on left, LSB on right.
Default instruction automatically loaded at power-up and in test-logic-reset state.
GS8322Z18/36/72(B/E/C)-xxxV
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05 6/2006
29/39
2002, GSI Technology
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