參數(shù)資料
型號： GS832272C-225
廠商： Electronic Theatre Controls, Inc.
英文描述： 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
中文描述： 200萬× 18，100萬× 36，為512k × 72分配36MB的S /雙氰胺同步突發(fā)靜態(tài)存儲器
文件頁數(shù)： 32/41頁
文件大小： 1223K
代理商： GS832272C-225
Preliminary
GS832218(B/E)/GS832236(B/E)/GS832272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.06 9/2004
32/41
2001, GSI Technology
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-
tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-
ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-
ated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-
Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
JTAG TAP Instruction Set Summary
Instruction
Code
Description
Notes
EXTEST
000
Places the Boundary Scan Register between TDI and TDO.
1
IDCODE
001
Preloads ID Register and places it between TDI and TDO.
1, 2
SAMPLE-Z
010
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Forces all RAM output drivers to High-Z.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
1
RFU
011
1
SAMPLE/
PRELOAD
100
1
GSI
101
GSI private instruction.
1
RFU
110
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
Places Bypass Register between TDI and TDO.
1
BYPASS
111
1
Notes:
1.
2.
Instruction codes expressed in binary, MSB on left, LSB on right.
Default instruction automatically loaded at power-up and in test-logic-reset state.
相關PDF資料
PDF描述
GS832272C-225I 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
GS832272C-250 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
GS832218 256K SERIAL CONFIGURATION PROM
GS832218B 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
GS832218B-133 256K SERIAL CONFIGURATION PROM
相關代理商/技術參數(shù)
參數(shù)描述
GS832272C-250I 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 2.5V/3.3V 36MBIT 512KX72 6.5NS/3NS 209FBGA - Trays
GS832272C-250I/T/R/COLLINS 制造商:GSI Technology 功能描述:512K X 72 (36 MEG) SYNCH BURST, SCD, JTAG, FLEXDRIVE - Tape and Reel
GS832272C-250IV 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V/2.5V 36MBIT 512KX72 6.5NS/3NS 209BGA - Trays
GS832272GC-133 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 2.5V/3.3V 36MBIT 512KX72 8.5NS/4NS 209FBGA - Trays
GS832272GC-133I 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 2.5V/3.3V 36MBIT 512KX72 8.5NS/4NS 209FBGA - Trays
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*