參數(shù)資料
型號(hào): GS832018T-250I
廠商: Electronic Theatre Controls, Inc.
元件分類: DRAM
英文描述: 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs
中文描述: 200萬(wàn)× 18,100萬(wàn)× 32,100萬(wàn)× 36同步突發(fā)靜態(tài)存儲(chǔ)器分配36MB
文件頁(yè)數(shù): 17/25頁(yè)
文件大小: 669K
代理商: GS832018T-250I
GS832018/32/36T-250/225/200/166/150/133
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 10/2004
17/25
2003, GSI Technology
Notes:
1.
2.
These parameters are sampled and are not 100% tested.
ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
AC Electrical Characteristics
Parameter
Symbol
-250
-225
-200
-166
-150
-133
Unit
Min
4.0
1.5
Max
2.5
Min
4.4
1.5
Max
2.7
Min
5.0
1.5
Max
3.0
Min
6.0
1.5
Max
3.5
Min
6.7
1.5
Max
3.8
Min
7.5
1.5
Max
4.0
Pipeline
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
tKC
tKQ
tKQX
ns
ns
ns
Clock to Output in Low-Z
tLZ
1
tS
tH
tKC
tKQ
tKQX
1.5
1.5
1.5
1.5
1.5
1.5
ns
Setup time
Hold time
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
1.2
0.2
6.5
3.0
6.5
1.3
0.3
7.0
3.0
7.0
1.4
0.4
7.5
3.0
7.5
1.5
0.5
8.0
3.0
8.0
1.5
0.5
8.5
3.0
8.5
1.5
0.5
8.5
3.0
8.5
ns
ns
ns
ns
ns
Flow
Through
Clock to Output in Low-Z
tLZ
1
tS
tH
tKH
tKL
3.0
3.0
3.0
3.0
3.0
3.0
ns
Setup time
Hold time
Clock HIGH Time
Clock LOW Time
Clock to Output in
High-Z
G to Output Valid
1.5
0.5
1.3
1.5
1.5
0.5
1.3
1.5
1.5
0.5
1.3
1.5
1.5
0.5
1.3
1.5
1.5
0.5
1.5
1.7
1.5
0.5
1.7
2
ns
ns
ns
ns
tHZ
1
1.5
2.5
1.5
2.7
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
ns
tOE
2.5
2.7
3.0
3.5
3.8
4.0
ns
G to output in Low-Z
tOLZ
1
0
0
0
0
0
0
ns
G to output in High-Z
tOHZ
1
2.5
2.7
3.0
3.0
3.0
3.0
ns
ZZ setup time
tZZS
2
5
5
5
5
5
5
ns
ZZ hold time
tZZH
2
tZZR
1
1
1
1
1
1
ns
ZZ recovery
20
20
20
20
20
20
ns
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