參數(shù)資料
型號(hào): GS816272CGC-30I
廠商: GSI TECHNOLOGY
英文描述: 256K x 72 18Mb S/DCD Sync Burst SRAMs
中文描述: 256 × 72 35.7的S /雙氰胺同步突發(fā)靜態(tài)存儲(chǔ)器
文件頁(yè)數(shù): 27/31頁(yè)
文件大?。?/td> 678K
代理商: GS816272CGC-30I
GS816272CC-333/300/250/200/150
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 2/2005
27/31
2004, GSI Technology
JTAG Port Timing Diagram
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
V
IHJ3
V
ILJ3
V
IHJ2
V
ILJ2
I
INHJ
I
INLJ
I
OLJ
V
OHJ
V
OLJ
V
OHJC
V
OLJC
Min.
Max.
V
DD3
+0.3
Unit Notes
3.3 V Test Port Input High Voltage
2.0
V
1
3.3 V Test Port Input Low Voltage
0.3
0.8
V
1
2.5 V Test Port Input High Voltage
0.6 * V
DD2
V
DD2
+0.3
0.3 * V
DD2
V
1
2.5 V Test Port Input Low Voltage
0.3
V
1
TMS, TCK and TDI Input Leakage Current
300
1
uA
2
TMS, TCK and TDI Input Leakage Current
1
100
uA
3
TDO Output Leakage Current
1
1
uA
4
Test Port Output High Voltage
1.7
V
5, 6
Test Port Output Low Voltage
0.4
V
5, 7
Test Port Output CMOS High
V
DDQ
– 100 mV
V
5, 8
Test Port Output CMOS Low
100 mV
V
5, 9
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Input Under/overshoot voltage must be
2 V > Vi < V
DDn
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.
V
ILJ
V
IN
V
DDn
0 V
V
IN
V
ILJn
Output Disable, V
OUT
= 0 to V
DDn
The TDO output driver is served by the V
DDQ
supply.
I
OHJ
=
4 mA
I
OLJ
= + 4 mA
I
OHJC
= –100 uA
I
OLJC
= +100 uA
tTH
tTS
tTKQ
tTH
tTS
tTH
tTS
tTKL
tTKH
tTKC
TCK
TDI
TMS
TDO
Parallel SRAM input
相關(guān)PDF資料
PDF描述
GS816272CGC-333 256K x 72 18Mb S/DCD Sync Burst SRAMs
GS816272CGC-333I 256K x 72 18Mb S/DCD Sync Burst SRAMs
GS816272C 256K x 72 18Mb Sync Burst SRAMs
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