參數(shù)資料
型號(hào): GS816272CC-200V
廠商: GSI TECHNOLOGY
元件分類: DRAM
英文描述: 256K x 72 18Mb S/DCD Sync Burst SRAMs
中文描述: 256K X 72 CACHE SRAM, 6.5 ns, PBGA209
封裝: 14 X 22 MM, 1 MM PITCH, BGA-209
文件頁數(shù): 25/29頁
文件大?。?/td> 851K
代理商: GS816272CC-200V
GS816272CC-xxxV
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02a 6/2006
25/29
2004, GSI Technology
JTAG Port Recommended Operating Conditions and DC Characteristics (1.8/2.5 V Version)
Parameter
Symbol
V
ILJ1
V
ILJ2
V
IHJ1
V
IHJ2
I
INHJ
I
INLJ
I
OLJ
V
OHJ
V
OLJ
V
OHJC
V
OLJC
Min.
Max.
0.3 * V
DD1
0.3 * V
DD2
V
DD1
+0.3
V
DD2
+0.3
Unit Notes
1.8 V Test Port Input Low Voltage
0.3
V
1
2.5 V Test Port Input Low Voltage
0.3
V
1
1.8 V Test Port Input High Voltage
0.6 * V
DD1
0.6 * V
DD2
V
1
2.5 V Test Port Input High Voltage
V
1
TMS, TCK and TDI Input Leakage Current
300
1
uA
2
TMS, TCK and TDI Input Leakage Current
1
100
uA
3
TDO Output Leakage Current
1
1
uA
4
Test Port Output High Voltage
1.7
V
5, 6
Test Port Output Low Voltage
0.4
V
5, 7
Test Port Output CMOS High
V
DDQ
– 100 mV
V
5, 8
Test Port Output CMOS Low
100 mV
V
5, 9
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Input Under/overshoot voltage must be
2 V < Vi < V
DDn
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.
V
ILJ
V
IN
V
DDn
0 V
V
IN
V
ILJn
Output Disable, V
OUT
= 0 to V
DDn
The TDO output driver is served by the V
DDQ
supply.
I
OHJ
=
4 mA
I
OLJ
= + 4 mA
I
OHJC
= –100 uA
I
OLJC
= +100 uA
JTAG Port AC Test Conditions
Notes:
1.
2.
Include scope and jig capacitance.
Test conditions as shown unless otherwise noted.
Parameter
Conditions
V
DD
– 0.2 V
0.2 V
1 V/ns
V
DDQ
/2
V
DDQ
/2
Input high level
Input low level
Input slew rate
Input reference level
Output reference level
DQ
V
DDQ
/2
50
30pF
*
JTAG Port AC Test Load
* Distributed Test Jig Capacitance
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