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參數(shù)資料
| 型號： | GS816218BB |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 1M x 18, 512K x 36 18MbS/DCD Sync Burst SRAMs |
| 中文描述： | 100萬× 18，為512k × 36 18MbS/DCD同步突發(fā)靜態(tài)存儲器 |
| 文件頁數(shù)： | 26/37頁 |
| 文件大?。?/td> | 866K |
| 代理商： | GS816218BB |
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ID Register Contents
Die
Revision
Code
Not Used
I/O
Configuration
GSI Technology
JEDEC Vendor
ID Code
P
0
1
1
Bit #
x36
x18
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
X
X
X
X
0
0
0
X
1
0
0
1
0
0
X
X
X
X
0
0
0
X
1
0
0
1
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0 1 1 0 1 1 0 0 1
0 1 1 0 1 1 0 0 1
GS816218/36B(B/D)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04 9/2005
26/37
2004, GSI Technology
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS816218BD-150 | 1M x 18, 512K x 36 18MbS/DCD Sync Burst SRAMs |
| GS816218BD-150I | 1M x 18, 512K x 36 18MbS/DCD Sync Burst SRAMs |
| GS816218BD-200 | 1M x 18, 512K x 36 18MbS/DCD Sync Burst SRAMs |
| GS816218BD-200I | 1M x 18, 512K x 36 18MbS/DCD Sync Burst SRAMs |
| GS816218BD-250 | 1M x 18, 512K x 36 18MbS/DCD Sync Burst SRAMs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS816218BB-150 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 3.3V 18MBIT 1MX18 7.5NS/3.8NS 119FBGA - Trays |
| GS816218BB-150I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 3.3V 18MBIT 1MX18 7.5NS/3.8NS 119FBGA - Trays |
| GS816218BB-150IV | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 18MBIT 1MX18 7.5NS/3.8NS 119FPBGA - Trays |
| GS816218BB-150V | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 18MBIT 1MX18 7.5NS/3.8NS 119FPBGA - Trays |
| GS816218BB-200 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 3.3V 18MBIT 1MX18 6.5NS/3NS 119FBGA - Trays |
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