參數(shù)資料
型號(hào): GS816218B-225I
廠商: GSI TECHNOLOGY
元件分類: DRAM
英文描述: 1M x 18, 512K x 36, 256K x 72 18Mb Sync Burst SRAMs
中文描述: 1M X 18 CACHE SRAM, 6 ns, PBGA119
封裝: FBGA-119
文件頁(yè)數(shù): 28/41頁(yè)
文件大?。?/td> 980K
代理商: GS816218B-225I
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GS816218(B/D)/GS816236(B/D)/GS816272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 2.17 11/2004
28/41
1999, GSI Technology
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
Instruction Register
ID Code Register
·
31 30 29
Boundary Scan Register
0
1
2
0
· · ·
1
2
0
Bypass Register
TDI
TDO
TMS
TCK
Test Access Port (TAP) Controller
1
·
1
0
·
·
·
·
·
·
·
·
·
Control Signals
·
相關(guān)PDF資料
PDF描述
GS816218B-250 1M x 18, 512K x 36, 256K x 72 18Mb Sync Burst SRAMs
GS816218B-250I 1M x 18, 512K x 36, 256K x 72 18Mb Sync Burst SRAMs
GS816218D-133 1M x 18, 512K x 36, 256K x 72 18Mb Sync Burst SRAMs
GS816218D-133I 1M x 18, 512K x 36, 256K x 72 18Mb Sync Burst SRAMs
GS816218D-150 1M x 18, 512K x 36, 256K x 72 18Mb Sync Burst SRAMs
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