參數(shù)資料
型號(hào)： GS8161Z36T-166T
廠(chǎng)商： Electronic Theatre Controls, Inc.
元件分類(lèi)： DRAM
英文描述： 4096 x 18 Synchronous FIFO Memory 64-TQFP 0 to 70
中文描述： 35.7流水線(xiàn)和流量，通過(guò)同步唑的SRAM
文件頁(yè)數(shù)： 26/36頁(yè)
文件大小： 939K
代理商： GS8161Z36T-166T
GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 2.15 11/2004
26/36
1998, GSI Technology
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
JTAG Tap Controller State Diagram
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-
tate testing of other devices in the scan path.
Select DR
Capture DR
0
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
1
Select IR
Capture IR
0
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
1
Test Logic Reset
Run Test Idle
0
1
0
1
1
0
1
1
1
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
1
1
1
1
相關(guān)PDF資料
PDF描述
GS8161Z36T-200 4096 x 18 Synchronous FIFO Memory 64-TQFP 0 to 70
GS8161Z36T-200I 4096 x 18 Synchronous FIFO Memory 64-TQFP 0 to 70
GS8161Z36T-200IT 4096 x 18 Synchronous FIFO Memory 64-TQFP 0 to 70
GS8161Z36T-200T 4096 x 18 Synchronous FIFO Memory 64-TQFP 0 to 70
GS8161Z36T-225 18Mb Pipelined and Flow Through Synchronous NBT SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8161Z36T-180 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:x36 Fast Synchronous SRAM
GS8161Z36T-180I 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:x36 Fast Synchronous SRAM
GS8161Z36T-180IT 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:x36 Fast Synchronous SRAM
GS8161Z36T-180T 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:x36 Fast Synchronous SRAM
GS8161Z36T-200 制造商:GSI 制造商全稱(chēng):GSI Technology 功能描述:18Mb Pipelined and Flow Through Synchronous NBT SRAM
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