參數(shù)資料
    

    


    


    
型號(hào)：
GS8161Z32T-225IT

    

    
廠商：
Electronic Theatre Controls, Inc.

    

    
英文描述：
18Mb Pipelined and Flow Through Synchronous NBT SRAM

    

    
中文描述：
35.7流水線和流量，通過(guò)同步唑的SRAM

    

    
文件頁(yè)數(shù)：
27/36頁(yè)

    

    
文件大?。?/td>
939K

    

    
代理商：
GS8161Z32T-225IT


    

    

    

	
    
    
    

    
    
	
    GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D)
    Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
    Rev:  2.15  11/2004
    27/36
     1998, GSI Technology
    SAMPLE/PRELOAD
    SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is 
    loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and 
    I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and 
    are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because 
    the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents 
    while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will 
    not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the 
    TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP 
    operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then 
    places the boundary scan register between the TDI and TDO pins. 
    EXTEST
    EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with 
    all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is 
    still determined by its input pins.
    Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. 
    Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output 
    drivers on the falling edge of TCK when the controller is in the Update-IR state.
    Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-
    tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-
    ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR 
    state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-
    ated. 
    IDCODE
    The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and 
    places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction 
    loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
    SAMPLE-Z
    If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-
    Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR 
    state.
    RFU
    These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
    
    
    
    
    
    


    


    

    相關(guān)PDF資料
    		

    PDF描述
    		

    
    

    
GS8161Z36T-225IT
18Mb Pipelined and Flow Through Synchronous NBT SRAM

    

    
GS8161Z18D-225IT
18Mb Pipelined and Flow Through Synchronous NBT SRAM

    

    
GS8161Z32D-225IT
18Mb Pipelined and Flow Through Synchronous NBT SRAM

    

    
GS8161Z36D-225IT
18Mb Pipelined and Flow Through Synchronous NBT SRAM

    

    
GS8161Z36D-150
18Mb Pipelined and Flow Through Synchronous NBT SRAM

    

    

    

    


    


    

    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
GS8161Z32T-225T
 制造商:GSI 制造商全稱:GSI Technology 功能描述:18Mb Pipelined and Flow Through Synchronous NBT SRAM

    

    
GS8161Z32T-250
 制造商:未知廠家 制造商全稱:未知廠家 功能描述:18Mb Pipelined and Flow Through Synchronous NBT SRAM

    

    
GS8161Z32T-250I
 制造商:GSI 制造商全稱:GSI Technology 功能描述:18Mb Pipelined and Flow Through Synchronous NBT SRAM

    

    
GS8161Z32T-250IT
 制造商:未知廠家 制造商全稱:未知廠家 功能描述:18Mb Pipelined and Flow Through Synchronous NBT SRAM

    

    
GS8161Z32T-250T
 制造商:GSI 制造商全稱:GSI Technology 功能描述:18Mb Pipelined and Flow Through Synchronous NBT SRAM

    

    
    
    
    
	
    	
    
    
     
     
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